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PIC24FJ256DA110 Datasheet(PDF) 4 Page - Microchip Technology |
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PIC24FJ256DA110 Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 408 page  PIC24FJ256DA210 FAMILY DS39969B-page 4 2010 Microchip Technology Inc. High-Performance CPU • Modified Harvard Architecture • Up to 16 MIPS Operation at 32 MHz • 8 MHz Internal Oscillator • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • Linear Program Memory Addressing, up to 12 Mbytes • Data Memory Addressing, up to 16 Mbytes: - 2K SFR space - 30K linear data memory - 66K extended data memory - Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory ( EDS) and EPMP (EDS is divided into 32-Kbyte pages) • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Power Management: • On-Chip Voltage Regulator of 1.8V • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run Mode: 800 A/MIPS, 3.3V Typical • Sleep mode Current Down to 20 A, 3.3V Typical • Standby Current with 32 kHz Oscillator: 22 A, 3.3V Typical Analog Features: • 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Operation is possible in Sleep mode - Band gap reference input feature • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Minimum time measurement setting at 100 ps • Available LVD Interrupt VLVD Level Special Microcontroller Features: • Operating Voltage Range of 2.2V to 3.6V • 5.5V Tolerant Input (digital pins only) • Configurable Open-Drain Outputs on Digital I/O Ports • High-Current Sink/Source (18 mA/18 mA) on all I/O Ports • Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up • Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, FRC oscillator • On-Chip LDO Regulator • Power-on Reset (POR) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) • Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words |
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