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CS61884-IQZ Datasheet(PDF) 3 Page - Cirrus Logic

Part No. CS61884-IQZ
Description  Octal T1/E1/J1 Line Interface Unit
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS61884
DS485F1
3
10.5 Loss-of-Signal (LOS) .......................................................................................................................27
10.6 Alarm Indication Signal (AIS) ..........................................................................................................28
11. JITTER ATTENUATOR .........................................................................................................................28
12. OPERATIONAL SUMMARY ..................................................................................................................29
12.1 Loopbacks .......................................................................................................................................29
12.2 Analog Loopback ............................................................................................................................29
12.3 Digital Loopback ..............................................................................................................................30
12.4 Remote Loopback ...........................................................................................................................30
13. HOST MODE ..........................................................................................................................................32
13.1 SOFTWARE RESET .......................................................................................................................32
13.2 Serial Port Operation .......................................................................................................................32
13.3 Parallel Port Operation ....................................................................................................................33
13.4 Register Set ....................................................................................................................................34
14. REGISTER DESCRIPTIONS .................................................................................................................35
14.1 Revision/IDcode Register (00h) ......................................................................................................35
14.2 Analog Loopback Register (01h) .....................................................................................................35
14.3 Remote Loopback Register (02h) ...................................................................................................35
14.4 TAOS Enable Register (03h) ..........................................................................................................35
14.5 LOS Status Register (04h) ..............................................................................................................35
14.6 DFM Status Register (05h) .............................................................................................................35
14.7 LOS Interrupt Enable Register (06h) ...............................................................................................36
14.8 DFM Interrupt Enable Register (07h) ..............................................................................................36
14.9 LOS Interrupt Status Register (08h) ................................................................................................36
14.10 DFM Interrupt Status Register (09h) .............................................................................................36
14.11 Software Reset Register (0Ah) .....................................................................................................36
14.12 Performance Monitor Register (0Bh) ............................................................................................36
14.13 Digital Loopback Reset Register (0Ch) .........................................................................................37
14.14 LOS/AIS Mode Enable Register (0Dh) ..........................................................................................37
14.15 Automatic TAOS Register (0Eh) ...................................................................................................37
14.16 Global Control Register (0Fh) .......................................................................................................38
14.17 Line Length Channel ID Register (10h) .........................................................................................38
14.18 Line Length Data Register (11h) ...................................................................................................39
14.19 Output Disable Register (12h) .......................................................................................................39
14.20 AIS Status Register (13h) .............................................................................................................39
14.21 AIS Interrupt Enable Register (14h) ..............................................................................................39
14.22 AIS Interrupt Status Register (15h) ...............................................................................................40
14.23 AWG Broadcast Register (16h) .....................................................................................................40
14.24 AWG Phase Address Register (17h) ............................................................................................40
14.25 AWG Phase Data Register (18h) ..................................................................................................40
14.26 AWG Enable Register (19h) ..........................................................................................................40
14.27 AWG Overflow Interrupt Enable Register (1Ah) ............................................................................41
14.28 AWG Overflow Interrupt Status Register (1Bh) .............................................................................41
14.29 JA Error Interrupt Enable Register (1Ch) ......................................................................................41
14.30 JA Error Interrupt Status Register (1Dh) .......................................................................................41
14.31 Bits Clock Enable Register (1Eh) ..................................................................................................41
14.32 Reserved Register (1Fh) ...............................................................................................................41
14.33 Status Registers ............................................................................................................................42
14.33.1 Interrupt Enable Registers ...................................................................................................42
14.33.2 Interrupt Status Registers ....................................................................................................42
15. ARBITRARY WAVEFORM GENERATOR ............................................................................................43
16. JTAG SUPPORT ....................................................................................................................................45
16.1 TAP Controller .................................................................................................................................45
16.1.1 JTAG Reset ...........................................................................................................................45




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