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CS4226 Datasheet(PDF) 9 Page - Cirrus Logic |
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CS4226 Datasheet(HTML) 9 Page - Cirrus Logic |
9 / 37 page CS4226 DS188F4 9 SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30 pF) Notes: 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL S/PDIF RECEIVER CHARACTERISTICS (RX1, RX2, RX3, RX4 pins only) Notes: 15. CLKOUT Jitter is for 256×FS selected as output frequency measured from falling edge to falling edge. Jitter is greater for 384×Fs and 512×Fs as selected output frequency. 16. For CLKOUT frequency equal to 1×Fs, 384×Fs, and 512×Fs. See Master Clock Output section. DIGITAL CHARACTERISTICS Parameter Symbol Min Max Units I2C® Mode (SPI/I2C = 1) SCL Clock Frequency fscl - 100 kHz Bus Free Time Between Transmissions tbuf 4.7 µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 µs Clock Low Time tlow 4.7 µs Clock High Time thigh 4.0 µs Setup Time for Repeated Start Condition tsust 4.7 µs SDA Hold Time from SCL Falling (Note 14) thdd 0 µs SDA Setup Time to SCL Rising tsud 250 ns Rise Time of Both SDA and SCL Lines tr 1 µs Fall Time of Both SDA and SCL Lines tf 300 ns Setup Time for Stop Condition tsusp 4.7 µs Parameter Symbol Min Typ Max Units Input Resistance ZN -10 - k Ω Input Voltage VTH 200 - - mVpp Input Hysteresis VHYST -50 - mV Input Sample Frequency FS 30 - 50 kHz CLKOUT Jitter (Note 15) - 200 - ps RMS CLKOUT Duty Cycle (high time/cycle time) (Note 16) 40 50 60 % Parameter Symbol Min Typ Max Units High-level Input Voltage (except RX1) VIH 2.8 - (VD+)+0.3 V Low-level Input Voltage (except RX1) VIL -0.3 - 0.8 V High-level Output Voltage at I0 = -2.0 mA VOH (VD+)-1.0 - - V Low-level Output Voltage at I0 = 2.0 mA VOL -- 0.4 V Input Leakage Current (Digital Inputs) - - 10 µA Output Leakage Current (High-Impedance Digital Outputs) - - 10 µA |
Similar Part No. - CS4226_04 |
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Similar Description - CS4226_04 |
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