 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CS5371 Datasheet(PDF) 10 Page - Cirrus Logic |
|
||||||||||||||||||||||||||||||
CS5371 Datasheet(HTML) 10 Page - Cirrus Logic |
|
|
10 / 22 page  CS5371 CS5372 10 DS255F3 small signals, reducing the gain requirements for input amplifier stages by a factor of two relative to single ended analog inputs. 4.2. Anti-alias Filters The CS5371/72 modulator inputs must be band- width limited to ensure modulator loop stability and to prevent aliased high-frequency signals. The modulators are 4th order and so are conditionally stable, and can be adversely affected by high am- plitude out-of-band signals. Also, aliasing effects degrade modulator performance if the analog in- puts are not bandwidth limited since out-of-band signals can appear in the measurement band- width. The use of a simple single pole low-pass anti-alias filter on the differential inputs ensures out-of-band signals are eliminated. Anti-alias filtering may be accomplished actively in an amplifier stage ahead of the CS5371/72 modu- lator, or passively using an RC filter across the dif- ferential rough and fine analog inputs. An RC filter is recommended, even when using an amplifier stage, as it minimizes the ‘charge kick’ that the driving amplifier sees as switched capacitor sam- pling is performed. The -3 dB corner of the input anti-alias filter should be set to the internal modulator sampling clock di- vided by 64. The modulator sampling clock is a di- vision by 4 of the modulator clock, MCLK. With MCLK=2.048 MHz the modulator sampling clock is 512 kHz, requiring an input filter with a -3 dB cor- ner at 8 kHz. MCLK Frequency = 2.048 MHz Sampling Frequency = MCLK / 4 = 512 kHz -3 dB Filter Corner = Sample Freq / 64 = 8 kHz RC filter = 8 kHz = 1 / [ 2 π * (2 * Rdiff) * Cdiff ] It should be noted that when using low power mode (LPWR=1 and MCLK=1.024 MHz) the mod- ulator sampling clock is 256 kHz, so the -3 dB filter corner should be scaled down to 4 kHz. MCLK Frequency = 1.024 MHz Sampling Frequency = MCLK / 4 = 256 kHz -3 dB Filter Corner = Sample Freq / 64 = 4 kHz RC filter = 4 kHz = 1 / [ 2 π * (2 * Rdiff) * Cdiff ] Figure 3 illustrates the CS5372/CS5376A system connections with input anti-alias filter components. Filter components on the rough and fine pins should be identical values for optimum perfor- mance, with the capacitor values a minimum of 0.02 µF. The rough input can use either X7R or C0G capacitors, while the fine input requires C0G type capacitors for optimal linearity. Using X7R ca- pacitors on the fine inputs will degrade signal to distortion performance up to 8 dB. 4.3. Input Impedance Due to the dynamic switched-capacitor input archi- tecture, the input current required from the analog signal source and thus the input impedance of the analog input pins changes any time MCLK is changed. The input impedance of the rough charge inputs, INR+ and INR-, is [1 / (f * C)] where f is the modulator clock frequency, MCLK, and C is the internal sampling capacitor. A 2.048 MHz modulator clock yields a rough input impedance of approximately [1 / (2.048 MHz)*(20 pF)], or about 24 k Ω. Internal to the modulator the rough charge inputs pre-charge the sampling capacitor used by the fine inputs, therefore the input current to the fine inputs is very low and the effective input impedance is or- ders of magnitude above the impedance of the rough inputs. 4.4. Maximum Signal Levels The CS5371/72 modulators are 4th order and are therefore conditionally stable, and may go into an oscillatory condition if the analog inputs over-range beyond full scale by more than 5%. If an unstable condition is detected, the modulators collapse to a 1st order system until loop stability is achieved. During this time, the MFLAG pin transitions from low to high signaling the digital filter to set an error bit in the digital output status word. The analog in- put signal must be reduced to within the full-scale range of the converter for at least 32 MCLK cycles for the modulators to recover from an unstable condition. 5. INPUT OFFSET The CS5371/72 modulators are ∆Σ type and so can produce ‘idle tones’ in the passband when the |
Similar Part No. - CS5371_05 |
|
Similar Description - CS5371_05 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
