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LM3S6952-IQC80-A2 Datasheet(PDF) 10 Page - Texas Instruments |
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LM3S6952-IQC80-A2 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 626 page Figure 15-1. I2C Block Diagram ............................................................................................. 398 Figure 15-2. I2C Bus Configuration ........................................................................................ 398 Figure 15-3. START and STOP Conditions ............................................................................. 399 Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 399 Figure 15-5. R/S Bit in First Byte ............................................................................................ 399 Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 400 Figure 15-7. Master Single SEND .......................................................................................... 403 Figure 15-8. Master Single RECEIVE ..................................................................................... 404 Figure 15-9. Master Burst SEND ........................................................................................... 405 Figure 15-10. Master Burst RECEIVE ...................................................................................... 406 Figure 15-11. Master Burst RECEIVE after Burst SEND ............................................................ 407 Figure 15-12. Master Burst SEND after Burst RECEIVE ............................................................ 408 Figure 15-13. Slave Command Sequence ................................................................................ 409 Figure 16-1. Ethernet Controller ............................................................................................. 434 Figure 16-2. Ethernet Controller Block Diagram ...................................................................... 434 Figure 16-3. Ethernet Frame ................................................................................................. 435 Figure 16-4. Interface to an Ethernet Jack .............................................................................. 440 Figure 17-1. Analog Comparator Module Block Diagram ......................................................... 481 Figure 17-2. Structure of Comparator Unit .............................................................................. 482 Figure 17-3. Comparator Internal Reference Structure ............................................................ 482 Figure 18-1. PWM Unit Diagram ............................................................................................ 493 Figure 18-2. PWM Module Block Diagram .............................................................................. 494 Figure 18-3. PWM Count-Down Mode .................................................................................... 495 Figure 18-4. PWM Count-Up/Down Mode .............................................................................. 495 Figure 18-5. PWM Generation Example In Count-Up/Down Mode ........................................... 496 Figure 18-6. PWM Dead-Band Generator ............................................................................... 496 Figure 19-1. QEI Block Diagram ............................................................................................ 531 Figure 19-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 532 Figure 20-1. 100-Pin LQFP Package Pin Diagram .................................................................. 547 Figure 20-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 548 Figure 23-1. Load Conditions ................................................................................................ 582 Figure 23-2. JTAG Test Clock Input Timing ............................................................................. 584 Figure 23-3. JTAG Test Access Port (TAP) Timing .................................................................. 585 Figure 23-4. JTAG TRST Timing ............................................................................................ 585 Figure 23-5. External Reset Timing (RST) .............................................................................. 586 Figure 23-6. Power-On Reset Timing ..................................................................................... 586 Figure 23-7. Brown-Out Reset Timing .................................................................................... 586 Figure 23-8. Software Reset Timing ....................................................................................... 586 Figure 23-9. Watchdog Reset Timing ..................................................................................... 587 Figure 23-10. Hibernation Module Timing ................................................................................. 588 Figure 23-11. ADC Input Equivalency Diagram ......................................................................... 589 Figure 23-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .................................................................................................... 590 Figure 23-13. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ................. 590 Figure 23-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ..................................... 591 Figure 23-15. I2C Timing ......................................................................................................... 592 Figure 23-16. External XTLP Oscillator Characteristics ............................................................. 594 Figure D-1. 100-Pin LQFP Package ...................................................................................... 622 April 05, 2010 10 Texas Instruments-Production Data Table of Contents |
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