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TMS320VC5505ZCH Datasheet(PDF) 9 Page - Texas Instruments |
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TMS320VC5505ZCH Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 135 page  TMS320VC5505 www.ti.com SPRS503B – JUNE 2009 – REVISED JANUARY 2010 Table 3-3. SARAM Blocks (continued) CPU DMA/USB CONTROLLER MEMORY BLOCK BYTE ADDRESS RANGE BYTE ADDRESS RANGE 030000h − 031FFFh 000B 0000h – 000B 1FFFh SARAM 16 032000h − 033FFFh 000B 2000h – 000B 3FFFh SARAM 17 034000h − 035FFFh 000B 4000h – 000B 5FFFh SARAM 18 036000h − 037FFFh 000B 6000h – 000B 7FFFh SARAM 19 038000h − 039FFFh 000B 8000h – 000B 9FFFh SARAM 20 03A000h − 03BFFFh 000B A000h – 000B BFFFh SARAM 21 03C000h − 03DFFFh 000B C000h – 000B DFFFh SARAM 22 03E000h − 03FFFFh 000B E000h – 000B FFFFh SARAM 23 040000h – 041FFFh 000C 0000h – 000C 1FFFh SARAM 24 042000h – 043FFFh 000C 2000h – 000C 3FFFh SARAM 25 044000h – 045FFFh 000C 4000h – 000C 5FFFh SARAM 26 046000h – 047FFFh 000C 6000h – 000C 7FFFh SARAM 27 048000h – 049FFFh 000C 8000h – 000C 9FFFh SARAM 28 04A000h – 04BFFFh 000C A000h – 000C BFFFh SARAM 29 04C000h – 04DFFFh 000C C000h – 000C DFFFh SARAM 30 04E000h – 04FFFFh 000C E000h – 000C FFFFh SARAM 31(1) (1) SARAM31 (byte address range: 0x4E000 – 0x4EFFF) is reserved for the bootloader. After the boot process is complete, this memory space can be used. 3.2.3 On-Chip Read-Only Memory (ROM) The zero-wait-state ROM is located at the byte address range FE0000h – FFFFFFh. The ROM is composed of four 16K-word blocks, for a total of 128K bytes of ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM. The standard VC5505 device includes a Bootloader program resident in the ROM. When the MPNMC bit field of the ST3 status register is cleared (by default), the byte address range FE0000h – FFFFFFh is reserved for the on-chip ROM. When the MPNMC bit field of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory map, and byte address range FE0000h – FFFFFFh is directed to external memory space. A hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset instruction does not affect the MPNMC bit. The ROM can be accessed by the program and data buses. Each on-chip ROM block is a one cycle per word access memory. 3.2.4 External Memory The external memory space of the device is located at the byte address range 050000h – FFFFFFh. The external memory space is divided into four chip select spaces: EMIF CS2 through CS5 space dedicated to asynchronous devices including flash. Each chip select space has a corresponding chip select pin (called EMIF_CSx) that is activated during an access to the chip select space. The external memory interface (EMIF) provides the means for the DSP to access external memories and other devices including: NOR Flash, NAND Flash, and SRAM. Before accessing external memory, you must configure the EMIF through its memory-mapped registers. The EMIF provides a configurable 16- or 8-bit data bus, an address bus width of up to 21-bits, and 4 dedicated chip selects, along with memory control signals. To maximize power savings, the I/O pin of the EMIF can be operated at an independent voltage from the rest of other I/O pins on the device. Copyright © 2009–2010, Texas Instruments Incorporated Device Overview 9 Submit Documentation Feedback Product Folder Link(s): TMS320VC5505 |
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