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ADS5400IPZP Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5400IPZP Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 48 page  ADS5400 SLAS611B – OCT 2009 – REVISED MARCH 2010 www.ti.com INTERLEAVING ADJUSTMENTS Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate = 1 GSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 1.5 VPP differential clock (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET ADJUSTMENTS Resolution 9 Bits LSB magnitude at full scale range of 2VPP 120 µV DNL Differential linearity error -2.5 2.5 LSB INL Integral Non-Linearity error -3 3 LSB Recommended Min Offset -8 mV Setting from default offset value, to maintain AC performance Recommended Max Offset 8 mV Setting GAIN ADJUSTMENTS Resolution 12 Bits LSB magnitude 120 µV DNL Differential linearity error -4 -2, +1 4 LSB INL Integral Non-Linearity error -8 -2, +4 8 LSB Min Gain Setting 1.52 VPP Max Gain Setting 2 VPP INPUT CLOCK FINE PHASE ADJUSTMENT Resolution 6 Bits LSB magnitude 116 fs DNL Differential linearity error -2 2.5 LSB INL Integral Non-Linearity error -2.5 4 LBS Max Fine Clock Skew setting 7.4 ps INPUT CLOCK COARSE PHASE ADJUSTMENT Resolution 5 Bits LSB magnitude 2.4 ps DNL Differential linearity error -1 1 LSB INL Integral Non-Linearity error -1 5 LSB Max Coarse Clock Skew 73 ps setting 8 Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): ADS5400 |
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