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ADS6424 Datasheet(PDF) 2 Page - Texas Instruments |
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ADS6424 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 71 page  www.ti.com Reference INA_P INA_M CLKP CLKM VCM DCLKP DCLKM ADS642x SHA FCLKP FCLKM INB_P INB_M SHA SHA SHA INC_P INC_M IND_P IND_M PLL BIT Clock FRAME Clock DA0_P DA1_P DA0_M DA1_M DB0_P DB1_P DB0_M DB1_M DC0_P DC1_P DC0_M DC1_M DD0_P DD1_P DD0_M DD1_M Serial Interface Parallel Interface 12-Bit ADC 12-Bit ADC 12-Bit ADC 12-Bit ADC Digital Encoder and Serializer Digital Encoder and Serializer Digital Encoder and Serializer Digital Encoder and Serializer B0199-04 ADS6424 ADS6423 ADS6422 SLAS532A – MAY 2007 – REVISED JUNE 2007 An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. ADS642X has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40 °C to 85°C). 2 Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): ADS6424 ADS6423 ADS6422 |
Similar Part No. - ADS6424_10 |
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Similar Description - ADS6424_10 |
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