ICM7555_2

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 02 — 3 August 2009

3 of 22

NXP Semiconductors

ICM7555

General purpose CMOS timer

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

Refer to Figure 1 “Functional diagram”.

7.1 Function selection

[1]

RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.

Fig 2.

Pin configuration for SO8

Fig 3.

Pin configuration for DIP8

DISCHARGE

THRESHOLD

CONTROL_VOLTAGE

GND

TRIGGER

OUTPUT

RESET

ICM7555CD

ICM7555ID

002aae400

1

2

3

4

6

5

8

7

ICM7555CN

ICM7555IN

GND

TRIGGER

DISCHARGE

OUTPUT

THRESHOLD

RESET

CONTROL_VOLTAGE

002aae401

1

2

3

4

6

5

8

7

Table 2.

Pin description

Symbol

Pin

Description

GND

1

supply ground

TRIGGER

2

start timer input; (active LOW)

OUTPUT

3

timer logic level output

RESET

4

timer inhibit input; (active LOW)

CONTROL_VOLTAGE

5

timing capacitor upper voltage sense input

THRESHOLD

6

timing capacitor lower voltage sense input

DISCHARGE

7

timing capacitor discharge output

8

supply voltage

Table 3.

Function selection

THRESHOLD voltage

TRIGGER voltage

RESET[1]

OUTPUT

Discharge switch

don’t care

don’t care

L

L

on

H

L

on

H

stable

stable

don’t care

H

H

off