ADS8331IPWR datasheet(8/40 Pages) TI

Part #	ADS8331IPWR

Description	Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface

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Manufacturer	TI [Texas Instruments]

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ADS8331

ADS8332

SBAS363 – DECEMBER 2009

www.ti.com

TIMING CHARACTERISTICS: VA = 5V

At TA = –40°C to +85°C, and VA = VBD = 5V, unless otherwise noted.

(1) (2)

PARAMETER

MIN

TYP

MAX

UNIT

External, fCCLK = 1/2 fSCLK

0.5

10.5

MHz

fCCLK Frequency, conversion clock, CCLK

Internal

10.9

11.5

12.6

MHz

tSU1

Setup time, rising edge of CS to EOC

1

CCLK

tH1

Hold time, rising edge of CS to EOC

20

ns

tWL1

Pulse duration, CONVST low

40

ns

tWH1

Pulse duration, CS high

40

ns

tSU2

Setup time, rising edge of CS to EOS

20

ns

tH2

Hold time, rising edge of CS to EOS

20

ns

tSU3

Setup time, falling edge of CS to first falling edge of SCLK

8

ns

tWL2

Pulse duration, SCLK low

12

tSCLK – 12

ns

tWH2

Pulse duration, SCLK high

11

tSCLK – 11

ns

I/O clock only

25

ns

I/O and conversion clocks

47.6

1000

ns

tSCLK Cycle time, SCLK

I/O clock, daisy-chain mode

25

ns

I/O and conversion clocks,

47.6

1000

ns

daisy-chain mode

tD1

Delay time, falling edge of SCLK to SDO invalid

10pF load

5

ns

tD2

Delay time, falling edge of SCLK to SDO valid

10pF load

20

ns

tD3

Delay time, falling edge of CS to SDO valid, SDO MSB output

10pF load

20

ns

tSU4

Setup time, SDI to falling edge of SCLK

8

ns

tH3

Hold time, SDI to falling edge of SCLK

8

ns

tD4

Delay time, rising edge of CS to SDO 3-state

10

ns

tSU5

Setup time, last falling edge of SCLK before rising edge of CS

10

ns

tD5

Delay time, falling edge of CS to deactivation of INT

20

ns

tD6

Delay time, CDI to SDO in daisy-chain mode

10pF load

20

ns

(1)

All input signals are specified with tr = tf = 1.5ns (10% to 90% of VBD) and timed from a voltage level of (VIL + VIH)/2.

(2)

See the Timing Diagrams section.

8

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