PIN ONE LOCATION PHD PACKAGE

16

15

OC_ADJ

14

RESET

13

C_STARTUP

12

INPUT_A

11

INPUT_B

10

VI_CM

9

GND

8

AGND

7

VREG

6

INPUT_C

5

INPUT_D

4

TEST

3

2

1

SD

64-pins QFP package

33

GND_D

34

GND_C

_

35

GND_C

36

OUT_C

37

OUT_C

38

PVDD_C

39

PVDD_C

40

BST_C

41

BST_B

42

PVDD_B

43

OUT_B

44

GND_B

45

GND_A

46

47

48

OTW1

PVDD_B

OUT_B

GND_B

DKD PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

M3

OC_ADJ

VDD

PSU_REF

M2

M1

READY

OTW

SD

NC

NC

TEST

INPUT_D

INPUT_C

VREG

AGND

GND

VI_CM

INPUT_B

INPUT_A

C_STARTUP

RESET

GND_C

OUT_A

BST_A

OUT_B

BST_B

PVDD_B

PVDD_A

BST_C

PVDD_C

OUT_C

GND_A

GND_B

OUT_D

PVDD_D

BST_D

GND_D

GVDD_AB

GVDD_CD

PVDD_A

PVDD_D

OUT_D

OUT_A

PHD PACKAGE

(TOP VIEW)

Electrical Pin 1

NC

NC

Pin 1 Marker

White Dot

44 pins PACKAGE

(TOP VIEW)

TAS5612A

SLAS710 – JUNE 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Terminal Assignment

Both package types contains a heat slug that is located on the top side of the device for convenient thermal

coupling to the heat sink.

2

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Copyright © 2010, Texas Instruments Incorporated

Product Folder Link(s): TAS5612A