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LPC3131 Datasheet(PDF) 11 Page - NXP Semiconductors |
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LPC3131 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 68 page  LPC3130_3131_1 © NXP B.V. 2009. All rights reserved. Preliminary data sheet Rev. 1 — 9 February 2009 11 of 68 NXP Semiconductors LPC3130/3131 Low-cost, low-power ARM926EJ-S microcontrollers [1] Digital I/O levels are explained in Table 5. [2] Cell types are explained in Table 6. [3] Pin can be configured as GPIO pin in the IOCONFIG block. [4] The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for UART flow control, they can also be selected to be used for an alternative function: SPI chip select signals (SPI_CS_OUT1 and SPI_CS_OUT2) External Bus Interface (NAND flash controller) EBI_A_0_ALE[3] B3 SUP4 DO O DIO4 EBI Address Latch Enable EBI_A_1_CLE[3] A2 SUP4 DO O DIO4 EBI Command Latch Enable EBI_D_0[3] G2 SUP4 DIO I DIO4 EBI Data I/O 0 EBI_D_1[3] F2 SUP4 DIO I DIO4 EBI Data I/O 1 EBI_D_2[3] F1 SUP4 DIO I DIO4 EBI Data I/O 2 EBI_D_3[3] E1 SUP4 DIO I DIO4 EBI Data I/O 3 EBI_D_4[3] E2 SUP4 DIO I DIO4 EBI Data I/O 4 EBI_D_5[3] D1 SUP4 DIO I DIO4 EBI Data I/O 5 EBI_D_6[3] D2 SUP4 DIO I DIO4 EBI Data I/O 6 EBI_D_7[3] C1 SUP4 DIO I DIO4 EBI Data I/O 7 EBI_D_8[3] B1 SUP4 DIO I DIO4 EBI Data I/O 8 EBI_D_9[3] A3 SUP4 DIO I DIO4 EBI Data I/O 9 EBI_D_10[3] A1 SUP4 DIO I DIO4 EBI Data I/O 10 EBI_D_11[3] C2 SUP4 DIO I DIO4 EBI Data I/O 11 EBI_D_12[3] G3 SUP4 DIO I DIO4 EBI Data I/O 12 EBI_D_13[3] D3 SUP4 DIO I DIO4 EBI Data I/O 13 EBI_D_14[3] E3 SUP4 DIO I DIO4 EBI Data I/O 14 EBI_D_15[3] F3 SUP4 DIO I DIO4 EBI Data I/O 15 EBI_DQM_0_NOE[3] H1 SUP4 DO O DIO4 NAND Read Enable (active LOW) EBI_NWE[3] J2 SUP4 DO O DIO4 NAND Write Enable (active LOW) NAND_NCS_0[3] J1 SUP4 DO O DIO4 NAND Chip Enable 0 NAND_NCS_1[3] J3 SUP4 DO O DIO4 NAND Chip Enable 1 NAND_NCS_2[3] K1 SUP4 DO O DIO4 NAND Chip Enable 2 NAND_NCS_3[3] K2 SUP4 DO O DIO4 NAND Chip Enable 3 mNAND_RYBN0[3] E6 SUP4 DI I DIO4 NAND Ready/Busy 0 mNAND_RYBN1[3] E7 SUP4 DI I DIO4 NAND Ready/Busy 1 mNAND_RYBN2[3] B4 SUP4 DI I DIO4 NAND Ready/Busy 2 mNAND_RYBN3[3] D4 SUP4 DI I DIO4 NAND Ready/Busy 3 EBI_NCAS_BLOUT_0[3] G1 SUP4 DO O DIO4 EBI Lower lane byte select (7:0) EBI_NRAS_BLOUT_1[3] H2 SUP4 DO O DIO4 EBI Upper lane byte select (15:8) Pulse Width Modulation module PWM_DATA[3] B9 SUP3 DO / GPIO O DIO1 PWM Output Table 4. Pin description Pin names with prefix m are multiplexed pins. See Table 10 for pin function selection of multiplexed pins. Pin name BGA Ball Digital I/O level [1] Application function Pin state after reset Cell Type [2] Description |
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