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FSEZ1317MY Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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FSEZ1317MY Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 17 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FSEZ1317 • Rev. 1.0.4 3 Marking Information Figure 4. Top Mark Pin Configuration Figure 5. SOP and Dip Pin Configuration Pin Definitions Pin # Name Description 1 CS Current Sense . This pin connects a current-sense resistor, to detect the MOSFET current for peak-current-mode control in CV mode, and provides the output-current regulation in CC mode. 2 VDD Power Supply . IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. 3 GND Ground 4 COMR Cable Compensation . This pin connects a 1µF capacitor between the COMR and GND pins for compensation voltage drop due to output cable loss in CV mode. 5 VS Voltage Sense . This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. 7 HV High Voltage . This pin connects to bulk capacitor for high-voltage startup. 8 DRAIN Driver Output . Power MOSFET drain. This pin is the high-voltage power MOSFET drain. F : Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP, N=DIP) P: Y=Green Package M: Manufacture Flow Code |
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