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MC9S08DZ96F2VLF Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc |
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MC9S08DZ96F2VLF Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc |
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3 / 458 page  8-Bit HCS08 Central Processor Unit (CPU) • 40-MHz HCS08 CPU (20-MHz bus) • HC08 instruction set with added BGND instruction • Support for up to 32 interrupt/reset sources On-Chip Memory • FLASH read/program/erase over full operating voltage and temperature • EEPROM in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; Program and Erase while executing FLASH; Erase abort • Random-access memory (RAM) Power-Saving Modes • Two very low power stop modes • Reduced power wait mode • Very low power real time interrupt for use in run, wait, and stop Clock Source Options • Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz • Multi-purpose Clock Generator (MCG) — PLL and FLL modes; reference clock with nonvolatile trim (0.2% resolution, 1.5% tolerance over temperature with internal temperature compensation); External reference with oscillator/resonator options System Protection • Watchdog computer operating properly (COP) reset with option to run from backup dedicated 1-kHz internal clock source or bus clock; with optional windowed operation • Low-voltage detection with reset or interrupt; selectable trip points • Illegal opcode detection with reset • Illegal address detection with reset • FLASH and EEPROM block protect • Loss-of-lock protection Development Support • Single-wire background debug interface • On-chip, in-circuit emulation (ICE) with real-time bus capture Peripherals • ADC — 24-channel, 12-bit resolution, 2.5 μs conversion time, automatic compare function, temperature sensor, internal bandgap reference channel • ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; runs in stop3 mode • MSCAN — CAN protocol - Version 2.0 A, B; standard and extended data frames; Support for remote frames; Five receive buffers with FIFO storage scheme; Flexible identifier acceptance filters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit • SCIx — Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended break generation; Slave extended break detection; Wakeup on active edge • SPIx — Up to two SPIs; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting • IICx — Up to two IICs; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; General Call Address; Interrupt driven byte-by-byte data transfer • TPMx — One 6-channel (TPM1), one 2-channel (TPM2) and one 4-channel (TPM3); Selectable input capture, output compare, or buffered edge- and center-aligned PWM on each channel. • RTC — (Real-time counter) 8-bit modulus counter with binary or decimal based prescaler; Real-time clock capabilities using external crystal and RTC for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components Input/Output • Up to 87 general-purpose input/output (I/O) pins and 1 input-only pin • Up to 32 interrupt pins with selectable polarity on each pin • Hysteresis and configurable pull device on all input pins. • Configurable slew rate and drive strength on all output pins. Package Options • 100-pin low-profile quad flat-pack(LQFP) — 14x14 mm • 64-pin low-profile quad flat-pack (LQFP) — 10x10 mm • 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm MC9S08 DZ128 MC9S08 DZ96 MC9S08 DV128 MC9S08 DV96 FLASH 128K 96K 128K 96K EEPROM 2K 2K — — RAM 8K 6K 6K 4K MC9S08DZ128 Series Features |
Similar Part No. - MC9S08DZ96F2VLF |
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