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PCA9543AD Datasheet(PDF) 7 Page - NXP Semiconductors

Part # PCA9543AD
Description  2-channel I2C-bus switch with interrupt logic and reset
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9543AD Datasheet(HTML) 7 Page - NXP Semiconductors

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PCA9543A_43B_43C_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 15 June 2009
7 of 23
NXP Semiconductors
PCA9543A/43B/43C
2-channel I2C-bus switch with interrupt logic and reset
Remark: Two interrupts can be active at the same time.
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A will reset
its registers and I2C-bus state machine and will deselect all channels. The RESET input
must be connected to VDD through a pull-up resistor.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9543A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9543A registers and I2C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9543A are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2C-bus to another.
Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 10 “Static characteristics” of this data
sheet). In order for the PCA9543A to act as a voltage translator, the Vo(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
(1) maximum
(2) typical
(3) minimum
Fig 8.
Pass gate voltage versus supply voltage
VDD (V)
2.0
5.5
4.5
3.0
4.0
002aaa964
3.0
2.0
4.0
5.0
Vo(sw)
(V)
1.0
3.5
5.0
2.5
(1)
(2)
(3)


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