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PCA9624BS Datasheet(PDF) 10 Page - NXP Semiconductors |
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PCA9624BS Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 37 page PCA9624_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 26 August 2009 10 of 37 NXP Semiconductors PCA9624 8-bit Fm+ I2C-bus 100 mA 40 V LED driver 7.3.1 Mode register 1, MODE1 [1] It takes 500 µs max. for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 µs window. [2] No blinking or dimming is possible when the oscillator is off. 7.3.2 Mode register 2, MODE2 [1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9624. Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only. Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access Value Description 7 AI2 read only 0 Register Auto-Increment disabled. 1* Register Auto-Increment enabled. 6 AI1 read only 0* Auto-Increment bit 1 = 0. 1 Auto-Increment bit 1 = 1. 5 AI0 read only 0* Auto-Increment bit 0 = 0. 1 Auto-Increment bit 0 = 1. 4 SLEEP R/W 0 Normal mode[1]. 1* Low power mode. Oscillator off[2]. 3 SUB1 R/W 0* PCA9624 does not respond to I2C-bus subaddress 1. 1 PCA9624 responds to I2C-bus subaddress 1. 2 SUB2 R/W 0* PCA9624 does not respond to I2C-bus subaddress 2. 1 PCA9624 responds to I2C-bus subaddress 2. 1 SUB3 R/W 0* PCA9624 does not respond to I2C-bus subaddress 3. 1 PCA9624 responds to I2C-bus subaddress 3. 0 ALLCALL R/W 0 PCA9624 does not respond to LED All Call I2C-bus address. 1* PCA9624 responds to LED All Call I2C-bus address. Table 6. MODE2 - Mode register 2 (address 01h) bit description Legend: * default value. Bit Symbol Access Value Description 7 - read only 0* reserved 6 - read only 0* reserved 5 DMBLNK R/W 0* group control = dimming. 1 group control = blinking. 4 INVRT R/W 0* reserved; write must always be a logic 0 3 OCH R/W 0* outputs change on STOP command[1] 1 outputs change on ACK 2 - R/W 1* reserved; write must always be a logic 1 1 - R/W 0* reserved; write must always be a logic 0 0 - R/W 1* reserved; write must always be a logic 1 |
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