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PCA9702PW Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCA9702PW Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 28 page PCA9701_PCA9702_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 11 November 2009 7 of 28 NXP Semiconductors PCA9701; PCA9702 18 V tolerant SPI 16-bit/8-bit GPI with INT 7.1.5 Register access timing Figure 6 shows the waveforms of the device operation. Initially CS is HIGH and SCLK is LOW. On the falling edge of CS, input port status, DATA[n:0] is captured into the input status register, and subsequently the first rising edge of SCLK parallel loads the shift register. The falling edge of SCLK samples the data on the SDIN. The MSB from the shift register is valid and available on the SDOUT after the first rising edge of SCLK. 7.2 Interrupt output INT is the open-drain interrupt output and is active LOW. A pull-up resistor of approximately 10 k Ω is recommended. The interrupt output is asserted when the input status is changed, and is cleared on the falling edge of CS or when the input port status matches the input status register. When there are multiple devices, the INT outputs may be tied together to a single pull-up. Table 3 illustrates the state of the interrupt output versus the state of the input port and input status register. The interrupt output is asserted when the input port and input status register differ. DATA[n:0] is data on the input pins, IN[n:0]. For 8-bit GPI (PCA9702), n = 7; for 16-bit GPI (PCA9701), n = 15. Shaded areas indicate active but invalid data. Fig 6. Register access timing CS SCLK SDIN SDOUT high-impedance MSB in MSB out 002aac426 MSB − 1 in MSB − 1 out LSB in LSB out input status register shift register DATA[n:0] DATA[n:0] sample SDIN |
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