PESD5V0U5BF_PESD5V0U5BV_1

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 01 — 15 August 2008

7 of 12

NXP Semiconductors

PESD5V0U5BF; PESD5V0U5BV

Ultra low capacitance bidirectional fivefold ESD protection arrays

7.

Application information

The PESD5V0U5BF and the PESD5V0U5BV are designed for the protection of up to five

bidirectional data or signal lines from the damage caused by ESD and surge pulses. The

devices may be used on lines where the signal polarities are both, positive and negative

with respect to ground.

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)

and surge transients. The following guidelines are recommended:

1. Place the device as close to the input terminal or connector as possible.

2. The path length between the device and the protected line should be minimized.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and

ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Ground planes should be used whenever possible. For multilayer PCBs, use ground

vias.

8.

Test information

8.1 Quality information

This product has been qualified in accordance with the Automotive Electronics Council

(AEC) standard

Q101 - Stress test qualification for discrete semiconductors, and is

suitable for use in automotive applications.

Fig 5.

Application diagram

006aab347

data- or transmission lines

DUT

1

2

3

5

4

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