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PH4025L Datasheet(PDF) 3 Page - NXP Semiconductors |
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PH4025L Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 12 page PH4025L_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 22 August 2007 3 of 12 NXP Semiconductors PH4025L N-channel TrenchMOS logic level FET Fig 1. Normalized total power dissipation as a function of mounting base temperature Fig 2. Normalized continuous drain current as a function of mounting base temperature Tmb =25 °C Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage Tmb (°C) 0 200 150 50 100 003aab937 40 80 120 Pder (%) 0 Tj (°C) 0 200 150 50 100 003aab555 40 80 120 Ider (%) 0 P der P tot P tot 25 °C () ------------------------ 100 % × = I der I D I D25 °C () -------------------- 100 % × = 003aab720 10 1 102 103 ID (A) 10−1 VDS (V) 10−1 102 10 1 DC 1 ms Limit RDSon = VDS/ID 10 ms 100 ms 100 µs tp = 10 µs |
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