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PH4830L Datasheet(PDF) 5 Page - NXP Semiconductors |
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PH4830L Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 12 page PH4830L_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 6 September 2007 5 of 12 NXP Semiconductors PH4830L N-channel TrenchMOS logic level FET 6. Characteristics Table 5. Characteristics Tj =25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS =0V Tj =25 °C 30 --V Tj = −55 °C 27 --V VGS(th) gate-source threshold voltage ID = 1 mA; VDS =VGS; see Figure 9 and 10 Tj =25 °C 1.3 1.7 2.15 V Tj = 150 °C 0.8 - - V Tj = −55 °C - - 2.6 V IDSS drain leakage current VDS = 30 V; VGS =0V Tj =25 °C - - 1.0 µA Tj = 150 °C - - 100 µA IGSS gate leakage current VGS = ±20 V; VDS = 0 V - - 100 nA RG gate resistance f = 1 MHz - 0.51 - Ω RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj =25 °C - 3.8 4.8 m Ω Tj = 150 °C - 6.3 7.7 m Ω VGS = 4.5 V; ID = 25 A; see Figure 6 and 8 - 5.6 7.0 m Ω Dynamic characteristics QG(tot) total gate charge ID = 25 A; VDS =12V; VGS = 4.5 V; see Figure 11 and 12 - 22.9 - nC QGS gate-source charge - 9.0 - nC QGS1 pre-VGS(th) gate-source charge - 5.5 - nC QGS2 post-VGS(th) gate-source charge - 3.5 - nC QGD gate-drain charge - 5.4 - nC VGS(pl) gate-source plateau voltage - 2.8 - V Ciss input capacitance VGS =0V; VDS = 12 V; f = 1 MHz; see Figure 14 -2786 -pF Coss output capacitance - 579 - pF Crss reverse transfer capacitance - 297 - pF Ciss input capacitance VGS =0V; VDS = 0 V; f = 1 MHz - 3300 - pF td(on) turn-on delay time VDS =12V; RL = 0.5 Ω; VGS = 4.5 V; RG = 5.6 Ω -28 - ns tr rise time -43 - ns td(off) turn-off delay time - 35 - ns tf fall time -19 - ns Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; see Figure 13 - 0.85 - V trr reverse recovery time IS = 20 A; dIS/dt = −100 A/µs; VGS =0V; VR =30V -47 - ns Qr recovered charge - 17 - nC |
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