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CDCE72010 Datasheet(PDF) 11 Page - Texas Instruments |
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CDCE72010 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 73 page AC/DC CHARACTERISTICS (CONTINUED) CDCE72010 www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009 over the specified industrial temperature range of –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT LVDS Hi Swing Output fclk Output frequency Open loop config. load, seeFigure 3 0 800 MHz |VOD| Differential output voltage RL =100 Ω 270 550 mV LVDS VOD magnitude ΔVOD 50 mV change VOS Offset voltage –40°C to 85°C 1.24 V ΔVOS VOS magnitude change 40 mV Short Circuit VOUT+ to VOUT = 0 27 mA ground Short Circuit VOUT– to VOUT = 0 27 mA ground Reference to output VCXO at 491.52MHz, Output 1 is divide by phase offset without using 16 and reference at 30.72MHz. M and N tpho (2) 14 ns available delay delays are fixed to one value. (Set to 0) PFD: adjustment 240kHz, (M and N = 128) tpd(LH)/ Propagation delay time, Crosspoint to crosspoint, load Figure 3 3.0 ns tpd(HL) VCXO_IN to output Divide by 1 for all dividers 45 Divide by 16 for all dividers 50 tsk(o) (3) LVDS output skew ps Divide by 1 for divider 1 2800 Divide by 16 for all other dividers Output capacitance on Y0 CO VCC = 3.3 V; VO = 0 V or VCC 5 pF to Y8 CO Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC 7 pF Power-down output IOPDH VO = VCC 25 µA current Power-down output IOPDL VO = 0V 5 µA current Duty cycle 45 55 % tr/tf Rise and fall time 20% to 80% of Voutpp 110 160 190 ps LVCMOS-TO-LVDS(4) Output skew between tskP_C LVCMOS and LVDS Crosspoint to VCC/2 0.9 1.4 1.9 ns outputs (1) All typical values are at VCC = 3.3 V, TA = 25°C. (2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and VCXO delay N). (3) The tsk(o) specification is only valid for equal loading of all outputs. (4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): CDCE72010 |
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