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PIC18LF45J50 Datasheet(PDF) 2 Page - Microchip Technology |
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PIC18LF45J50 Datasheet(HTML) 2 Page - Microchip Technology |
2 / 12 page PIC18F46J50 FAMILY DS80436C-page 2 2010 Microchip Technology Inc. TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Issue Summary Affected Revisions(1) A2 A4 MSSP I2C™ Modes 1. Must keep LATB<5:4> bits clear. X MSSP I2C Slave 2. Module may not receive the correct data if there is a delay in reading SSPxBUF after SSPxIF interrupt. XX EUSART Enable/Dis- able 3. If interrupts are enabled, a 2 TCY delay needed after re-enabling the module. XX A/D FOSC/2 Clock 4. FOSC/2 A/D Conversion mode may not meet linearity error limits. XX PMP PSP 5. Incorrect data capture in Slave modes. X Low-Power modes Deep Sleep 6. Wake-up events that occur during Deep Sleep entry may not generate an event. XX DC Characteristics Supply Volt- age 7. Minimum operating voltage (VDD) parameter for “F” devices is 2.25V. X A/D Band Gap Reference 8. At high VDD voltages, performing an A/D conversion on Channel 15 could have issues. XX CTMU Constant Current 9. Low voltages turn off constant current source. X Note 1: Only those issues indicated in the last column apply to the current silicon revision. |
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