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591R148M352DG Datasheet(PDF) 3 Page - Silicon Laboratories |
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591R148M352DG Datasheet(HTML) 3 Page - Silicon Laboratories |
3 / 12 page Si590/591 Preliminary Rev. 0.25 3 Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units LVPECL Output Option1 VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP LVDS Output Option2 VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP CML Output Option2 VO mid-level — VDD – 0.75 — V VOD swing (diff) 0.70 0.95 1.20 VPP CMOS Output Option3 VOH 0.8 x VDD — VDD V VOL —— 0.4 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL =15pF — 2 — ns Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff) LVDS: 1.25 V (diff) CMOS: VDD/2 45 — 55 % Notes: 1. 50 to V DD – 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF. Sinking or sourcing 12 mA for VDD = 3.3V, 6mA for VDD = 2.5V, 3mA for VDD = 1.8 V. Table 4. CLK± Output Phase Jitter Parameter Symbol Test Condition Min Typ Max Units Phase Jitter (RMS)1 for 50 MHz < FOUT < 525 MHz (LVPECL/LVDS/CML) J 12 kHz to 20 MHz — 0.5 1.0 ps Phase Jitter (RMS)2 for 50 MHz < FOUT < 160 MHz (CMOS) J 12 kHz to 20 MHz — 0.6 1.0 ps Notes: 1. Differential Modes LVPECL/LVDS/CML. 3.3 and 2.5 V supply voltage options only. 2. Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment. 3.3 V supply voltage option only. Table 5. CLK± Output Period Jitter Parameter Symbol Test Condition Min Typ Max Units Period Jitter* JPER RMS — — 3 ps Peak-to-Peak — — 35 *Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information. |
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