0-273-141-043 Datasheet(PDF) 11 Page - List of Unclassifed Manufacturers
ETC2 [List of Unclassifed Manufacturers]
Triaxial, digital acceleration sensor
30 May 2008
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Note: Specifications within this document are subject to change without notice.
3.1 Operational registers
The SPI4 bit ((address 15h, bit 7) is used to select the correct SPI protocol (three-wire or four-
wire, SPI-mode 3). The default value stored in the non-volatile part of the memory is SPI4=1
(four-wire SPI is default value !). After power on reset or soft reset or writing to EEPROM the
SPI4 EEPROM setting (35h) is downloaded to the image register SPI4 and the corresponding
SPI protocol is selected.
If the desired SPI is three-wire, the microcontroller must first write SPI4 to 0 (in image register
only or in EEPROM). This first writing is possible because only CSB, SCK and SDI are required
for a write sequence and the 3 bit timing diagrams are identical in three-wire and four-wire
Since EEPROM has limited write cycle lifetime (minimum 1000 cycles specified) it is
recommended to use one of the following procedures.
Procedure 1 (recommended): Set SPI4 in image to correct value (SPI4=0 for SPI three-wire,
SPI4=1 for SPI four-wire (=default)) every time after power on reset, soft reset or
EEPROM write command.
Procedure 2: Verify chip-ID (address 00h) after every power on reset, soft reset or EEPROM
write command to be chip_ID=02h. If chip_ID=FFh or chip_ID=00h unlock
EEPROM (section 3.3.3) and set SPI4 to correct interface in EEPROM at 35h.
Lock EEPROM. Optionally verify chip_ID after delay of >30ms.
Procedure 3: Set SPI4 once to correct interface in the EEPROM at 35h during final test
procedure at customer.
These two bits (address 14h, bits 4 and 3) are used to select the full scale acceleration range.
Directly after changing the full scale range it takes 1/(2*bandwidth) to overwrite the data
registers with filtered data according to the selected bandwidth.
Table 3: Settings of full scale range register
Full scale acceleration range
Not authorised code
Please refer to the comment in chapter 3 of how to protect bits 5, 6 and 7 when modifying other
bits of register 14h.
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