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PSMN085-150K Datasheet(PDF) 3 Page - NXP Semiconductors |
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PSMN085-150K Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 13 page PSMN085-150K_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 March 2010 3 of 13 NXP Semiconductors PSMN085-150K N-channel TrenchMOS SiliconMAX standard level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 150 V VGS gate-source voltage -20 20 V ID drain current Tsp =80 °C; see Figure 1 and 3 -3.5 A IDM peak drain current Tsp =25 °C; tp ≤ 10 µs; pulsed; see Figure 3 -40 A Ptot total power dissipation Tsp =80 °C; see Figure 2 -3.5 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Source-drain diode IS source current Tsp =80 °C - 3.1 A ISM peak source current Tsp =25 °C; tp ≤ 10 µs; pulsed - 40 A Fig 1. Normalized continuous drain current as a function of solder point temperature Fig 2. Normalized total power dissipation as a function of solder point temperature Tsp (°C) 0 200 150 50 100 03aa25 40 80 120 Ider (%) 0 Tsp (°C) 0 200 150 50 100 03aa17 40 80 120 Pder (%) 0 |
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