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PTN3360B Datasheet(PDF) 7 Page - NXP Semiconductors |
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PTN3360B Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 22 page PTN3360B_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 October 2009 7 of 22 NXP Semiconductors PTN3360B Enhanced performance HDMI/DVI level shifter [1] HVQFN48 package supply ground is connected to both GND pins and exposed center pad. GND pins must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. OUT_D1+ 22 TMDS differential output HDMI compliant TMDS output. OUT_D1+ makes a differential pair with OUT_D1 −. OUT_D1+ is in phase with IN_D1+. OUT_D1 − 23 TMDS differential output HDMI compliant TMDS output. OUT_D1 − makes a differential pair with OUT_D1+. OUT_D1 − is in phase with IN_D1−. HPD and DDC signals HPD_SINK 30 5 V CMOS single-ended input 0 V to 5 V (nominal) input signal. This signal comes from the DVI or HDMI sink. A HIGH value indicates that the sink is connected; a LOW value indicates that the sink is disconnected. HPD_SINK is pulled down by an integrated 200 k Ω pull-down resistor. HPD_SOURCE 7 3.3 V CMOS single-ended output 0 V to 3.3 V (nominal) output signal. This is level-shifted non-inverted version of the HPD_SINK signal. SCL_SOURCE 9 single-ended 3.3 V open-drain DDC I/O 3.3 V source-side DDC clock I/O. Pulled up by external termination to 3.3 V. SDA_SOURCE 8 single-ended 3.3 V open-drain DDC I/O 3.3 V source-side DDC data I/O. Pulled up by external termination to 3.3 V. SCL_SINK 28 single-ended 5 V open-drain DDC I/O 5 V sink-side DDC clock I/O. Pulled up by external termination to 5V. SDA_SINK 29 single-ended 5 V open-drain DDC I/O 5 V sink-side DDC data I/O. Pulled up by external termination to 5 V. DDC_EN 32 3.3 V CMOS input Enables the DDC buffer and level shifter. When DDC_EN = LOW, buffer/level shifter is disabled. When DDC_EN = HIGH, buffer and level shifter are enabled. Supply and ground VDD 2, 11, 15, 21, 26, 33, 40, 46 3.3 V DC supply Supply voltage; 3.3 V ± 10 %. VCC - GND[1] 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 ground Supply ground. All GND pins must be connected to ground for proper operation. Feature control signals REXT 6 analog I/O Current sense port used to provide an accurate current reference for the differential outputs OUT_Dx. For best output voltage swing accuracy, use of a 10 k Ω resistor (1 % tolerance) from this terminal to GND is recommended. May also be left open-circuit or tied to either VDD or GND. See Section 6.2 for details. Miscellaneous n.c. 3, 4, 10, 34, 35 no connection to the die Not connected. May be left open-circuit or tied to GND or VDD either directly or via a resistor. Table 2. Pin description …continued Symbol Pin Type Description |
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