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SC16C2552B Datasheet(PDF) 9 Page - NXP Semiconductors |
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SC16C2552B Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 38 page SC16C2552B_3 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 — 12 February 2009 9 of 38 NXP Semiconductors SC16C2552B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs 6.6 DMA operation The SC16C2552B FIFO trigger level provides additional flexibility to the user for block mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an empty location(s). The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA mode is de-activated (DMA Mode 0), the SC16C2552B activates the interrupt output pin for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1), the user takes the advantage of block mode operation by loading or unloading the FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2552B sets the interrupt output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level. 6.7 Loopback mode The internal loopback capability allows on-board diagnostics. In the Loopback mode, the normal modem interface pins are disconnected and reconfigured for loopback internally. MCR[3:0] register bits are used for controlling loopback diagnostic testing. In the Loopback mode, INT enable and MCR[2] in the MCR register (bits 3:2) control the modem RI and CD inputs, respectively. MCR signals DTR (bit 0) and RTS (bit 1) are used to control the modem DSR and CTS inputs, respectively. The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected together internally (see Figure 4). The CTS, DSR, CD, and RI are disconnected from their normal modem control inputs pins, and instead are connected internally to RTS, DTR, OP2 and OP1. Loopback test data is entered into the transmit holding register via the user data bus interface, D0 to D7. The transmit UART serializes the data and passes the serial data to the receive UART via the internal loopback connection. The receive UART converts the serial data back into parallel data that is then Table 5. Baud rate generator programming table using a 1.8432 MHz clock Output baud rate Output 16 × clock divisor (decimal) Output 16 × clock divisor (HEX) DLM program value (HEX) DLL program value (HEX) 50 2304 900 09 00 75 1536 600 06 00 150 768 300 03 00 300 384 180 01 80 600 192 C0 00 C0 1200 96 60 00 60 2400 48 30 00 30 4800 24 18 00 18 7200 16 10 00 10 9600 12 0C 00 0C 19.2 k 6 06 00 06 38.4 k 3 03 00 03 57.6 k 2 02 00 02 115.2 k 1 01 00 01 |
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