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SC28L92 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # SC28L92
Description  3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter (DUART)
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC28L92 Datasheet(HTML) 2 Page - NXP Semiconductors

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SC28L92_7
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
2 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
2.
Features
I Member of IMPACT family: 3.3 V to 5.0 V, −40 °C to +85 °C and 68xxx or 80xxx bus
interface for all devices
I Dual full-duplex independent asynchronous receiver/transmitters
I 16 character FIFOs for each receiver and transmitter
I Pin programming selects 68xxx or 80xxx bus interface
I Programmable data format
N 5 data to 8 data bits plus parity
N Odd, even, no parity or force parity
N 1 stop, 1.5 stop or 2 stop bits programmable in 116-bit increments
I 16-bit programmable counter/timer
I Programmable baud rate for each receiver and transmitter selectable from:
N 28 fixed rates: 50 kBd to 230.4 kBd
N Other baud rates to 1 MHz at 16×
N Programmable user-defined rates derived from a programmable counter/timer
N External 1× or 16× clock
I Parity, framing, and overrun error detection
I False start bit detection
I Line break detection and generation
I Programmable channel mode
N Normal (full-duplex)
N Automatic echo
N Local loopback
N Remote loopback
N Multi-drop mode (also called wake-up or 9-bit)
I Multi-function 7-bit input port (includes IACKN)
N Can serve as clock or control inputs
N Change of state detection on four inputs
N Inputs have typically > 100 kΩ pull-up resistors
N Change of state detectors for modem control
I Multi-function 8-bit output port
N Individual bit set/reset capability
N Outputs can be programmed to be status/interrupt signals
N FIFO status for DMA interface
I Versatile interrupt system
N Single interrupt output with eight maskable interrupting conditions
N Output port can be configured to provide a total of up to six separate interrupt
outputs that may be wire ORed
N Each FIFO can be programmed for four different interrupt levels
N Watchdog timer for each receiver
I Maximum data transfer rates: 1× - 1 Mbit/s, 16× - 1 Mbit/s
I Automatic wake-up mode for multi-drop applications
I Start-end break interrupt/status
I Detects break which originates in the middle of a character


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