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The device can handle HDCP based on 1.2 features.

Fig 1.

Block diagram

001aag595

2

× 12-bit YCbCr 4 : 2 : 2 semi-planar

1

× 12-bit YCbCr 4 : 2 : 2 ITU656

3

× 8-bit RGB or YCbCr 4 : 4 : 4

2

× 12-bit YCbCr 4 : 2 : 2 semi-planar

1

× 12-bit YCbCr 4 : 2 : 2 ITU656

TDA9984AHW

DOWN-

SAMPLER

4 : 4 : 4

to

4 : 2 : 2

VIDEO

INPUT

PROCESSOR

COLOR

SPACE

CONVERTER

RGB to YCbCr

YCbCr to RGB

UPSAMPLER

4 : 2 : 2

to

4 : 4 : 4

UPSCALER

4 : 2 : 2

AUDIO

PROCESSING

CLOCK

MANAGMENT

AUDIO

FIFO

CTS/N

AUDIO CONTENT

AUDIO INFO-FRAME

ACR

VIDEO INFO-FRAME

OTHER INFO-FRAME

HPD

MANAGEMENT

RxSENSE

INT

HPD

INTERRUPT

GENERATION

DATA

ISLAND

PACKET

INSERTION

VHREF GENERATOR

TMDS

SERIALIZER

26

TXC

−

27

TXC+

29

TX0

−

30

TX0+

32

TX1

−

33

TX1+

35

TX2

−

36

TX2+

SLAVE

HDCP

PROCESSING

OTP

MEMORY

KEYS

I2C_SCL I2C_SDA

DDC_SDA DDC_SCL

A0

A1

43

44

19

20

17

18

41

40

HARD

RESET

RST_N

42

3

13, 48, 71

14, 47,

72

60, 73

22

46, 15

25, 31,

37

39

59, 74

23

28, 34

38

16, 45

VPA[7:0]

VPB[7:0]

VPC[7:0]

VSYNC/VREF

HSYNC/HREF

DE/FREF

2

1

80

68 to 70

75 to 79

57, 58

61 to 65,

67

49 to 56

VCLK

AP0 to AP7

4 to 11

TM

21

ACLK

12

66

DDC BUS

MASTER

EXT_SWING

24