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BR35H160FJ-WCE2 Datasheet(PDF) 10 Page - Rohm

Part # BR35H160FJ-WCE2
Description  125??SPI BUS ICs BR35 Family
Download  17 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BR35H160FJ-WCE2 Datasheet(HTML) 10 Page - Rohm

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Technical Note
10/16
BR35H□□□-WC Series
www.rohm.com
2011.03 - Rev.C
© 2011 ROHM Co., Ltd. All rights reserved.
Method to cancel each command
READ
Cancellation method: cancel by CSB = “H”
RDSR
Cancellation method: cancel by CSB = “H”
WRITE, PAGE WRITE
a:Ope code, address input area.
Cancellation possible by CSB=”H”
b:Data input area (D7~D1 input area)
Cancellation possible by CSB=”H”
c:Data input area (D0 area)
Write starts after CSB rise.
After CSB rise, cancellation is no longer possible.
d:tE/W area.
Cancellation is possible by CSB = “H”. However, when
write starts (CSB rise) in area c, cancellation is no
longer possible. Also, cancellation is not possible by
continues inputting of SCK clock. In page write
mode, there is a write enable area at every 8 clocks.
Note 1) If Vcc is set to OFF during execution of write the data of the designated address is not guaranteed. Please
execute write again.
Note 2) If CSB rises at the same timing as that the SCK rises, write execution / cancel will become unstable.
Therefore, it is recommended to let CSB rise in the SCK = “L” area. As for SCK rise, ensure a timing of tCSS /
tCSH or higher.
WREN/WRDI
a:From ope code to 7-th clock rise, cancel by CSB = “H”.
b:Cancellation is not possible when CSB rises after the 7-th clock.
Fig.41 RDSR cancel valid timing
Fig.43 WREN/WRDI cancel valid timing
Ope code
Address
Cancel available in all areas of read mode
Data
8 bits
8 bits/16bits
8 bits
Ope code
Cancel available in all
areas of rdsr mode
Data
8 bits
8 bits
Fig.40 READ cancel valid timing
Ope code
Address
a
Data
tE/W
b
d
c
8bits
16bits
8bits
D7
b
D6
D5
D4
D3
D2
D1
D0
SCK
SI
c
Fig.42 WRITE cancel valid timing
8 bits
6
7
8
a
b
SCK


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