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BR35H128FVT-WCTR Datasheet(PDF) 3 Page - Rohm |
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BR35H128FVT-WCTR Datasheet(HTML) 3 Page - Rohm |
3 / 17 page Technical Note 3/16 BR35H□□□-WC Series www.rohm.com 2011.03 - Rev.C © 2011 ROHM Co., Ltd. All rights reserved. ● Pin Assignment and Description ● Operating Timing Characteristics ● Sync data input / output timing (Ta=-40℃ to +125℃, unless otherwise specified, load capacitance CL1=100pF) Parameter Symbol 2.5≦Vcc≦5.5V Unit Min. Typ. Max. SCK frequency fSCK - - 5 MHz SCK high time tSCKWH 85 - - ns SCK low time tSCKWL 85 - - ns CSB high time tCS 85 - - ns CSB setup time tCSS 90 - - ns CSB hold time tCSH 85 - - ns SCK setup time tSCKS 90 - - ns SCK hold time tSCKH 90 - - ns SI setup time tDIS 20 - - ns SI hold time tDIH 30 - - ns Data output delay time1 tPD1 - - 70 ns Data output delay time2 (CL2=30pF) tPD2 - - 55 ns Output hold time tOH 0 - - ns Output disable time tOZ - - 100 ns SCK rise time tRC - - 1 μs SCK fall time *1 tFC - - 1 μs OUTPUT rise time tRO - - 50 ns OUTPUT fall time tFO - - 50 ns Write time tE/W - - 5 ms *1 NOT 100% TESTED ● AC measurement conditions Parameter Symbol Limits Unit Min. Typ. Max. Load capacitance 1 CL1 - - 100 pF Load capacitance 2 CL2 - - 30 pF Input rise time - - - 50 ns Input fall time - - - 50 ns Input voltage - 0.2Vcc / 0.8Vcc V Input / Output judgment voltage - 0.3Vcc / 0.7Vcc V ● tOZ measurement condition IL is the load current that changes the SO voltage to 0.5×Vcc. IL = ±1mA. After CSB starts to rise, the time needed for SO to change to High-Z is defined with 10% changing point from SO=High or SO=Low. Terminal Name Input/Output Function Vcc – Power Supply to be connected GND – All input / output reference voltage, 0V CSB Input Chip select input SCK Input Serial clock input SI Input Start bit, ope code, address, and serial data input SO Output Serial data output NC – Non connection Vcc NC SCK SI CSB SO NC GND BR35H160-WC BR35H320-WC BR35H640-WC BR35H128-WC Fig.2 Pin Assignment Diagram Fig.3 Input timing CSB SCK SI SO tCS tCSS tSCKS tSCKWL tSCKWH tDIS tDIH tRC tFC High-Z Data through SI enters the IC in sync with the data rise edge of SCK. Please input address and data starting from the most significant bit MSB. CSB SCK SI SO tPD tOH tRO,tFO tOZ tCSH tSCKH tCS High-Z Fig.4 Input / Output timing Data through SO is output in sync with the data fall edge of SCK. Data is output starting from the most significant bit MSB. Vcc NC SCK SI CSB SO NC GND CL1=100pF IL=±1mA 0.7Vcc 0.2Vcc 0.9Vcc 0.1Vcc 0.8Vcc 0.5Vcc High Low CSB SO Signal Input Signal Input Signal Input Fig.5 tOZ measurement circuit Fig.6 tOZ measurement timing |
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