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BR24S04FJ-WE2 Datasheet(PDF) 10 Page - Rohm

Part # BR24S04FJ-WE2
Description  High Reliability Series EEPROMs I2C BUS
Download  41 Pages
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Manufacturer  ROHM [Rohm]
Direct Link  http://www.rohm.com
Logo ROHM - Rohm

BR24S04FJ-WE2 Datasheet(HTML) 10 Page - Rohm

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Technical Note
10/40
www.rohm.com
2009.09 - Rev.D
© 2009 ROHM Co., Ltd. All rights reserved.
BR24L□□-W Series,BR24S□□□-W Series
Write Command
Write cycle
Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
Fig.36 Byte write cycle (BR24L01A/02/04/08/16-W)
Fig.37 Byte write cycle (BR24L32/64-W)
Fig.38 Page write cycle (BR24L01A/02/04/08/16-W)
Fig.39 Page write cycle (BR24L32/64-W)
Data is written to the address designated by word address (n-th address)
By issuing stop bit after 8bit data input, write to memory cell inside starts.
When internal write is started, command is not accepted for tWR (5ms at maximum).
By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24L01A-W, BR24L02-W)
: Up to 16bytes (BR24L04-W, BR24L08-W,BR24L16-W)
: Up to 32bytes (BR24L32-W, BR24L64-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P9/32.)
As for page write cycle of BR24L01A-W and BR24L02-W, after the significant 5 bits (4 significant bits in BR24L01-W) of
word address are designated arbitrarily, and as for page write command of BR24L04-W, BR24L08-W, and BR24L16-W,
after page select bit (PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the
address of insignificant 4 bits (insignificant 3 bit in BR24L01A-W, and BR24L02-W) is incremented internally, and data
up to 16 bytes (up to 8 bytes in BR24L01A-W and BR24L02-W) can be written.
As for page write cycle of BR24L32-W and BR24L64-W, after the significant 7 bits (in the case of BR24L32-W) of word
address, or the significant 8 bits (in the case of BR24L64-W) of word address are designated arbitrarily, by continuing data
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
Note)
Fig.40 Difference of slave address of each type
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
WO R D
ADD R ESS(n)
DATA (n)
SDA
LIN E
A
C
K
A
C
K
D A TA(n+15)
A
C
K
SLAVE
ADDR ESS
1 0
0
1A 0
A1
A2
WA
7
D0
D7
D 0
WA
0
Note)
*1
*2
A1
A2
WA
7
D7
1
1
0
0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
WORD
ADDRESS
DATA
SLAVE
ADDRESS
A0
WA
0
D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
*1
*1 As for WA7, BR24L01A-W becomes Don’t care.
A1
A2
1
1
0
0
W
R
I
T
E
S
T
A
R
T
R
/
W
S
T
O
P
1st WORD
ADDRESS
DATA
SLAVE
ADDRESS
A0
D0
A
C
K
SDA
LINE
A
C
K
A
C
K
Note)
WA
12
WA
11
*
WA
0
A
C
K
2nd WORD
ADDRESS
D7
*1
*
*
*1 As for WA12, BR24L32-W becomes Don’t care.
*1 As for WA7, BR24L01A-W becomes Don’t care.
*2 As for BR24L01A/02-W becomes (n+7).
*1 As for WA12, BR24L32-W becomes Don’t care.
W
R
I
T
E
S
T
A
R
T
R
/
W
A
C
K
S
T
O
P
1st W O R D
AD D R ESS(n)
SD A
LIN E
A
C
K
A
C
K
D A TA (n+31)
A
C
K
SLAVE
AD D R ESS
1 0
0
1A 0
A1
A2
D0
Note)
*1
DA TA (n)
D0
D7
A
C
K
2nd W O R D
A D D R ESS(n)
WA
0
WA
12
WA
11
*
*
*
1 0
0
1A 0
A1
A2
*1 *2 *3
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and BR24L16-W, A0 becomes P0.


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