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TLV70025DCKT Datasheet(PDF) 2 Page - Texas Instruments |
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TLV70025DCKT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 30 page TLV700xx TLV701xx SLVSA00A – SEPTEMBER 2009 – REVISED APRIL 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT (2) TLV700xx yyy z XX is nominal output voltage (for example, 28 = 2.8 V). TLV701xx yyy z YYY is the package designator. Z is tape and reel quantity (R = 3000, T = 250). (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. (2) Output voltages from 0.7 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability. ABSOLUTE MAXIMUM RATINGS (1) At TJ = –40°C to +125°C (unless otherwise noted). All voltages are with respect to GND. PARAMETER TLV700xx/TLV701xx UNIT Input voltage range, VIN –0.3 to +6.0 V Enable voltage range, VEN –0.3 to +6.0 V Output voltage range, VOUT –0.3 to +6.0 V Maximum output current, IOUT Internally limited Output short-circuit duration Indefinite Total continuous power dissipation, PDISS See Dissipation Ratings Table Human body model (HBM) 2 kV ESD rating Charged device model (CDM) 500 V Operating junction temperature range, TJ –55 to +150 °C Storage temperature range, TSTG –55 to +150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DISSIPATION RATINGS DERATING FACTOR BOARD PACKAGE RqJC RqJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C Low-K(1) DCK 165°C/W 395°C/W 2.5 mW/°C 250 mW 140 mW 100 mW High-K(2) DCK 165°C/W 315°C/W 3.2 mW/°C 320 mW 175 mW 130 mW High-K(2) DSE 67°C/W 180°C/W 4.55 mW/°C 555 mW 305 mW 222 mW Low-K(1) DDC 90°C/W 280°C/W 3.6 mW/°C 360 mW 200 mW 145 mW High-K(2) DDC 90°C/W 200°C/W 5.0 mW/°C 500 mW 275 mW 200 mW (1) The JEDEC low-K (1s) board used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. 2 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated |
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