1Gbps to 14Gbps, SFP+ Multirate Limiting

Amplifier and VCSEL Driver

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7

ELECTRICAL CHARACTERISTICS (continued)

put load is AC-coupled to differential 100

otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-

ments. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SDA Setup Time

100

ns

SDA Hold Time

100

ns

SCL Rise to SDA Propagation

Time

5ns

CSEL Pulse-Width Low

500

ns

CSEL Leading Time Before the

First SCL Edge

500

ns

CSEL Trailing Time After the

Last SCL Edge

500

ns

SDA, SCL External Load

Total bus capacitance on one line with

4.7k

20

pF

Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-

put and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from

the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50

Ω load resistors to a separate

supply voltage.

Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-

istic jitter caused by this filter is not included in the DJ generation specifications.

Note 4: Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1.

8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum

of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ).

between two amplitudes: Signal_ON and Signal_OFF.

1) Receiver operates at sensitivity level plus 1dB power penalty.

a) Signal_OFF = 0

Signal_ON = (+8dB) + 10log(min_assert_level)

b) Signal_ON = (+1dB) + 10log(max_deassert_level)

Signal_OFF = 0

2) Receiver operates at overload.

Signal_OFF = 0

max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting.

10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is

defined as the arithmetic sum of PWD and PDJ.