Electronic Components Datasheet Search |
|
11AA011-ICS16K Datasheet(PDF) 9 Page - Microchip Technology |
|
11AA011-ICS16K Datasheet(HTML) 9 Page - Microchip Technology |
9 / 44 page 2010 Microchip Technology Inc. Preliminary DS22067H-page 9 11AAXXX/11LCXXX 3.6 Device Standby The 11XX features a low-power Standby mode during which the device is waiting to begin a new command. A high-to-low transition on SCIO will exit low-power mode and prepare the device for receiving the start header. Standby mode will be entered upon the following conditions: • A NoMAK followed by a SAK (i.e., valid termina- tion of a command) • Reception of a standby pulse 3.7 Device Idle The 11XX features an Idle mode during which all serial data is ignored until a standby pulse occurs. Idle mode will be entered upon the following conditions: • Invalid device address • Invalid command byte, including Read, CRRD, Write, WRSR, SETAL and ERAL during a write cycle. • Missed edge transition • Reception of a MAK following a WREN, WRDI, SETAL, or ERAL command byte • Reception of a MAK following the data byte of a WRSR command An invalid start header will indirectly cause the device to enter Idle mode. Whether or not the start header is invalid cannot be detected by the slave, but will prevent the slave from synchronizing properly with the master. If the slave is not synchronized with the master, an edge transition will be missed, thus causing the device to enter Idle mode. 3.8 Synchronization At the beginning of every command, the 11XX utilizes the start header to determine the master’s bus clock period. This period is then used as a reference for all subsequent communication within that command. The 11XX features re-synchronization circuitry which will monitor the position of the middle data edge during each MAK bit and subsequently adjust the internal time reference in order to remain synchronized with the master. There are two variables which can cause the 11XX to lose synchronization. The first is frequency drift, defined as a change in the bit period, TE. The second is edge jitter, which is a single occurrence change in the position of an edge within a bit period, while the bit period itself remains constant. 3.8.1 FREQUENCY DRIFT Within a system, there is a possibility that frequencies can drift due to changes in voltage, temperature, etc. The re-synchronization circuitry provides some toler- ance for such frequency drift. The tolerance range is specified by two parameters, FDRIFT and FDEV. FDRIFT specifies the maximum tolerable change in bus fre- quency per byte. FDEV specifies the overall limit in fre- quency deviation within an operation (i.e., from the end of the start header until communication is terminated for that operation). The start header at the beginning of the next operation will reset the re-synchronization cir- cuitry and allow for another FDEV amount of frequency drift. 3.8.2 EDGE JITTER Ensuring that edge transitions from the master always occur exactly in the middle or end of the bit period is not always possible. Therefore, the re-synchronization cir- cuitry is designed to provide some tolerance for edge jitter. The 11XX adjusts its phase every MAK bit, so TIJIT specifies the maximum allowable peak-to-peak jitter relative to the previous MAK bit. Since the position of the previous MAK bit would be difficult to measure by the master, the minimum and maximum jitter values for a system should be considered the worst-case. These values will be based on the execution time for different branch paths in software, jitter due to thermal noise, etc. The difference between the minimum and maximum values, as a percentage of the bit period, should be cal- culated and then compared against TIJIT to determine jitter compliance. Note: In the case of the WRITE, WRSR, SETAL, or ERAL commands, the write cycle is initiated upon receipt of the NoMAK, assuming all other write requirements have been met. Note: Because the 11XX only re-synchronizes during the MAK bit, the overall ability to remain synchronized depends on a combi- nation of frequency drift and edge jitter (i.e., if the MAK bit edge is experiencing the max- imum allowable edge jitter, then there is no room for frequency drift). Conversely, if the frequency has drifted to the maximum amount tolerable within a byte, then no edge jitter can be present. |
Similar Part No. - 11AA011-ICS16K |
|
Similar Description - 11AA011-ICS16K |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |