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PIC18LF27J53 Datasheet(PDF) 5 Page - Microchip Technology |
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PIC18LF27J53 Datasheet(HTML) 5 Page - Microchip Technology |
5 / 586 page 2010 Microchip Technology Inc. Preliminary DS39964B-page 5 PIC18F47J53 FAMILY Pin Diagrams 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 22 21 MCLR RA0/AN0/C1INA/ULPWU/RP0 RA1/AN1/C2INA/VBG/RP1 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ VDDCORE/VCAP RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 VSS1 OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI/RP11 RC1/CCP8/T1OSI/UOE/RP12 RC2/AN11/C2IND/CTPLS/RP13 VUSB RB7/CCP7/KBI3/PGD/RP10 RB6/CCP6/KBI2/PGC/RP9 RB5/CCP5/KBI1/SDI1/SDA1/RP8 RB4/CCP4/KBI0/SCK1/SCL1/RP7 RB3/AN9/C3INA/CTED2/VPO/RP6 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5 RB1/AN10/C3INC/RTCC/RP4 RB0/AN12/C3IND/INT0/RP3 VDD VSS2 RC7/CCP10/RX1/DT1/SDO1/RP18 RC6/CCP9/TX1/CK1/RP17 RC5/D+/VP RC4/D-/VM 28-Pin SPDIP/SOIC/SSOP 28-Pin QFN 10 11 2 3 6 1 18 19 20 21 22 12 13 14 15 8 7 16 17 23 24 25 26 27 28 9 PIC18F2XJ53 5 4 RB3/AN9/C3INA/CTED2/VPO/RP6 RB2/AN8/C2INC/CTED1/VMO/REFO/RP5 RB1/AN10/C3INC/RTCC/RP4 RB0/AN12/C3IND/INT0/RP3 VDD VSS2 RC7/CCP10/RX1/DT1/SDO1/RP18 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ VDDCORE/VCAP RA5/AN4/C1INC/SS1/HLVDIN/RCV/RP2 VSS1 OSC1/CLKI/RA7 OSC2/CLKO/RA6 Legend: Shaded pins are 5.5V tolerant. RPn represents remappable pins. Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS mod- ule, see Section 10.7 “Peripheral Pin Select (PPS)”. Note: For the QFN package, it is recommended that the bottom pad be connected to VSS. |
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