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LMP7312MAX Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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LMP7312MAX Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 22 page Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but for which specific performance is not guaranteed. For guaranteed specifications and the test conditions, see Electrical Characteristics. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22–A115–A (ESD MM std. of JEDEC). Field- Induced Charge-Device Model, applicable std. JESD22–C101–C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(max), θJA. The maximum allowable power dissipation at any ambient temperature is: PD(max) = (TJ (max) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that T J = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > T A. Note 5: Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: All limits are guaranteed by testing, design, or statistical analysis. Note 7: Offset voltage temperature drift is determined by dividing the change in V OS at the temperature extremes by the total temperature change. Note 8: V OCM_OS is the difference between the Output Common mode voltage (+VOUT+(-VOUT/VR))/2 and the Voltage on the VOCM pin. Note 9: The number specified is the average of rising and falling slew rates and is measured at 90% to 10%. Note 10: Load for these tests is shown in the Test Circuit Diagram. www.national.com 4 |
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