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I.MX27 Datasheet(PDF) 27 Page - Freescale Semiconductor, Inc |
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I.MX27 Datasheet(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 148 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.5 Freescale Semiconductor 27 Signal Descriptions 3 Signal Descriptions This section discusses the following: • Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be organized by group, as applicable. • Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data sheet requires them to be included here. Table 3 shows the i.MX27/MX27L signal descriptions. Table 3. i.MX27/MX27L Signal Descriptions Pad Name Function/Notes External Bus/Chip Select (EMI) A [13:0] Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for SDRAM/MDDR is not the address but the pre-charge bank select signal. MA10 Address bus signals for SDRAM/MDDR A [25:14] Address bus signals, shared with WEIM and PCMCIA SDBA[1:0] SDRAM/MDDR bank address signals SD[31:0] Data bus signals for SDRAM, MDDR SDQS[3:0] MDDR data sample strobe signals DQM0–DQM3 SDRAM data mask strobe signals EB0 Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG. EB1 Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD. OE Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR. CS [5:0] Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default CSD [1:0] is selected. DTACK is multiplexed with CS4. CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21. ECB Active low input signal sent by flash device to the EIM whenever the flash device must terminate an on-going burst sequence and initiate a new (long first access) burst sequence. LBA Active low signal sent by flash device causing external burst device to latch the starting burst address. BCLK Clock signal sent to external synchronous memories (such as burst flash) during burst mode. RW RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal is also shared with the PCMCIA PC_WE. RAS SDRAM/MDDR Row Address Select signal CAS SDRAM/MDDR Column Address Select signal SDWE SDRAM Write Enable signal SDCKE0 SDRAM Clock Enable 0 |
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