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I.MX27 Datasheet(PDF) 51 Page - Freescale Semiconductor, Inc

Part # I.MX27
Description  Multimedia Applications Processor
Download  148 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

I.MX27 Datasheet(HTML) 51 Page - Freescale Semiconductor, Inc

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i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
51
Electrical Characteristics
HCLK = AHB System Clock, THCLK = Period for HCLK, Tp = Period of CSI_PIXCLK
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold
time and setup time based on the following assumptions:
Rising-edge latch data:
max rise time allowed = (positive duty cyclehold time)
max fall time allowed = (negative duty cyclesetup time)
In most of case, duty cycle is 50/50, therefore:
max rise time = (period/2hold time)
max fall time = (period/2setup time)
For example: Given pixel clock period = 10 ns, duty cycle = 50/50, hold time = 1 ns, setup time = 1 ns.
positive duty cycle = 10/2 = 5 ns
max rise time allowed = 5 –1 = 4 ns
negative duty cycle = 10/2 = 5 ns
max fall time allowed = 5 –1 = 4 ns
Falling-edge latch data:
max fall time allowed = (negative duty cyclehold time)
max rise time allowed = (positive duty cyclesetup time)
4.2.5.2
Non-Gated Clock Mode Timing
In non-gated mode only, the VSYNC, and PIXCLK signals are used; the HSYNC signal is ignored. Figure
3 and Figure 4 show the different clock edge timing of CSI and Sensor in Non-Gated Mode. Table 3 is the
parameter value. Figure 11 and Figure 12 show the non-gated clock mode timings of CSI, and Table 22
lists the timing parameters.
Table 21. Gated Clock Mode Timing Parameters
Number
Parameter
Minimum
Maximum
Unit
1
csi_vsync to csi_hsync
9*THCLK
—ns
2
csi_hsync to csi_pixclk
3
(Tp/2)-3
ns
3
csi_d setup time
1
ns
4
csi_d hold time
1
ns
5
csi_pixclk high time
THCLK
—ns
6
csi_pixclk low time
THCLK
—ns
7
csi_pixclk frequency
0
HCLK/2
MHz


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