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i.MX27L Datasheet(PDF) 88 Page - Freescale Semiconductor, Inc |
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i.MX27L Datasheet(HTML) 88 Page - Freescale Semiconductor, Inc |
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88 / 148 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.5 88 Freescale Semiconductor Electrical Characteristics NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on AUDMUX pads when SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. For internal Frame Sync operation using external clock, the FS timing is the same as that of Tx Data, for example, during the AC97 mode of operation. 4.3.11.3 SSI Transmitter Timing with External Clock Figure 49 and Figure 50 show the SSI transmitter timing with external clock, and Table 48 lists the timing parameters. Figure 49. SSI Transmitter with External Clock Timing Diagram SS49 Oversampling clock rise time — 3 ns SS50 Oversampling clock low period 6 — ns SS51 Oversampling clock fall time — 3 ns Table 47. SSI Receiver with Internal Clock Timing Parameters (continued) ID Parameter Min Max Unit SS45 SS33 SS24 SS26 SS25 SS23 AD1_TXC AD1_TXFS (bl) AD1_TXFS (wl) AD1_TXD AD1_RXD Note: SRXD Input in Synchronous mode only SS31 SS29 SS27 SS22 SS44 SS39 SS38 SS37 SS46 (Input) (Input) (Input) (Output) (Input) |
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