HCS12DBFAMILYPP/D

Features

MOTOROLA

HCS12DB Family Product Proposal

3

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Seven or eight PWM channels with programmable period and duty cycle

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8-bit 4-channel or 16-bit 2-channel (80-Pin Version)

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8-bit 8-channel or 16-bit 4-channel (112-Pin Version)

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Separate control for each pulse width and duty cycle

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Center- or left-aligned outputs

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Programmable clock select logic with a wide range of frequencies

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Serial interfaces

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Two asynchronous serial communications interfaces (SCI)

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Up to two synchronous serial peripheral interfaces (SPI)

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Byteflight

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10 MBit/s serial protocol

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SIM (system integration module)

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CRG (windowed COP watchdog, real-time interrupt, clock monitor,

clock generation and reset)

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MEBI (multiplexed external bus interface)

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MMC (memory map and interface)

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INT (interrupt control)

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BKP (breakpoints)

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BDM (background debug mode)

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Clock generation

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Phase-locked loop clock frequency multiplier

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Limp home mode in absence of external clock

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Slow mode divider

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Low power 0.5 to 40 MHz crystal oscillator reference clock

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Operating frequency

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50 MHz equivalent to 25 MHz bus speed for single chip

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40 MHz equivalent to 20 MHz bus speed in expanded bus modes

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Internal 5 V to 2.5 V regulator

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112-Pin LQFP or 80-Pin QFP package

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I/O lines with 5-V input and drive capability

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5-V ATD inputs

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Dual supply (5 V for I/O and ATD, 2.5 V for logic

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Development support

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Single-wire background debug™ mode (BDM)

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On-chip hardware breakpoints

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com