BQ29440DRBT datasheet(2/15 Pages) TI

Part #	BQ29440DRBT

Description	Voltage Protection for 2-Series, 3-Series, or 4-Series Cell Li-Ion Batteries (Second-Level Protection)

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Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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bq29440, bq2944L0

bq29449, bq2944L9

SLUSA15B – MARCH 2010 – REVISED JUNE 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION(1)

TA

PART NUMBER

OUT PIN

PACKAGE

OVP

ORDERING INFORMATION(2)

LATCH

DESIGNATOR

MARKING

TAPE AND REEL

OPTION

(LARGE)(3)

(SMALL)(4)

-40°C

BQ29440

No

QFN-8

DRB

440

4.35 V

BQ29440DRBR

BQ29440DRBT

to

BQ2944L0

Yes

44L0

4.35 V

BQ2944L0DRBR

BQ2944L0DRBT

+85°C

BQ29449

No

449

4.30 V

BQ29449DRBR

BQ29449DRBT

BQ2944L9

Yes

44L9

4.30 V

BQ2944L9DRBR

BQ2944L9DRBT

(1)

Example: bq2944L0DRBR is a device with the OUT latch option with a VOV threshold of 4.35 V.

Contact Texas Instruments for other VOV threshold options.

(2)

For the most current package and ordering information, see the Package Addendum at the end of this document, or the TI website at

www.ti.com.

(3)

Large tape and reel quantity is 3,000 units.

(4)

Small tape and reel quantity is 250 units.

THERMAL INFORMATION

bq2944x

THERMAL METRIC(1)

DRB

UNITS

8 PINS

qJA

Junction-to-ambient thermal resistance(2)

50.5

qJC(top)

Junction-to-case(top) thermal resistance (3)

25.1

qJB

Junction-to-board thermal resistance (4)

19.3

°C/W

yJT

Junction-to-top characterization parameter (5)

0.7

yJB

Junction-to-board characterization parameter (6)

18.9

qJC(bottom)

Junction-to-case(bottom) thermal resistance (7)

5.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5)

The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7).

(7)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

PIN FUNCTIONS

PIN NAME

PIN NO.

DESCRIPTION

CD

6

Connection to external capacitor for programmable delay time

GND

4

Ground pin

OUT

8

Output

VC1

1

Sense voltage input for top cell

VC2

2

Sense voltage input for second-to-top cell

VC3

3

Sense voltage input for third-to-top cell

VC4

5

Sense voltage input for fourth-to-top cell (bottom cell)

VDD

7

Power supply

2

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Product Folder Link(s): bq29440 bq2944L0 bq29449 bq2944L9

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