TPS7A80xx

www.ti.com

SBVS135A – JUNE 2010 – REVISED JUNE 2010

THERMAL INFORMATION

TPS7A80xx

UNITS

8 PINS

47.8

83.0

N/A

°C/W

2.1

17.8

12.1

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.

(2)

Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the

JESD51 series. The following assumptions are used in the simulations:

(a) The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array.

(b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.

(c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To

understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction

Temperature sections.

(3)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(4)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(5)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(6)

(7)

(8)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Copyright © 2010, Texas Instruments Incorporated

Submit Documentation Feedback

3