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LTC694CN8-PBF Datasheet(PDF) 7 Page - Linear Technology

Part # LTC694CN8-PBF
Description  Microprocessor Supervisory Circuits
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC694CN8-PBF Datasheet(HTML) 7 Page - Linear Technology

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LTC690/LTC691
LTC694/LTC695
7
690fe
PIN FUNCTIONS
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Logic Output for μP Reset Control. Whenever
VCC falls below either the reset voltage threshold (4.65V,
typically) or VBATT,RESETgoesactivelow.AfterVCCreturns
to 5V, reset pulse generator forces RESET to remain active
low for a minimum of 35ms for the LTC690 /LTC691 (140ms
for the LTC694/LTC695). When the watchdog timer is
enabled but not serviced prior to a preset timeout period,
reset pulse generator also forces RESET to active low for a
minimum of 35ms for the LTC690/LTC691 (140ms for the
LTC694/5) for every preset timeout period (see Figure 11).
The reset active time is adjustable on the LTC691/LTC695.
An external pushbutton reset can be used in connection with
the RESET output. See Pushbutton Reset in Applications
Information section.
RESET: RESET is an active high logic ouput. It is the
inverse of RESET.
LOW LINE:LogicOutputfromComparatorC1.LOW⎯LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.65V typically),
LOW⎯LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW⎯LINE returns high (see Figure 1).
LOW⎯LINE goes low when VCC drops below VBATT (see
Table 1).
WDI: Watchdog Input, WDI, is a three level input. Driving
WDI either high or low for longer than the watchdog timeout
period, forces both RESET and WDO low. Floating WDI
disables the watchdog timer. The timer resets itself with
each transition of the watchdog input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
timeout period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW⎯LINE goes
low. The watchdog timer can be disabled by floating WDI
(see Figure 11).
CE IN: Logic input to the Chip⎯Enable gating circuit. CE IN
can be derived from microprocessor’s address line and/or
decoder output. See Applications Information section and
Figure 5 for additional information.
CE OUT: Logic Output on the Chip⎯Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is
a buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is high
or floating, the internal oscillator sets the reset active time
and watchdog timeout period. Forcing OSC SEL low, allows
OSC IN be driven from an external clock signal or external
capacitor be connected between OSC IN and GND.
OSC IN: Oscillator Input. OSC IN can be driven by
an external clock signal or external capacitor can be
connected between OSC IN and GND when OSC SEL is
forced low. In this configuration the nominal reset active
time and watchdog timeout period are determined by the
number of clocks or set by the formula (see Applications
Information section). When OSC SEL is high or floating,
the internal oscillator is enabled and the reset active time
is fixed at 50ms typical for the LTC691 and 200ms typical
for the LTC695. OSC IN selects between the 1.6 seconds
and 100ms typical watchdog timeout periods. In both
cases, the timeout period immediately after a reset is 1.6
seconds typical.


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