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DS92LV0421 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DS92LV0421 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 40 page Pin Name Pin # I/O, Type Description LVCMOS Outputs LOCK 27 O, LVCMOS LOCK Status Output LOCK = 1, PLL is locked, output stated determined by OEN. LOCK = 0, PLL is unlocked, output states determined by OSS_SEL and OEN. See Table 5. Control and Configuration PDB 1 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Device is enabled (normal operation). Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Device is powered down When the Device is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. VODSEL 33 I, LVCMOS w/ pull-down Parallel LVDS Driver Output Voltage Select — Pin or Register Control VODSEL = 1, LVDS VOD is ±450 mV, 900 mVp-p (typ) — Long Cable / De-E Applications VODSEL = 0, LVDS VOD is ±300 mV, 600 mVp-p (typ) OEN 30 I, LVCMOS w/ pull-down Output Enable. See Table 5. OSS_SEL 35 I, LVCMOS w/ pull-down Output Sleep State Select Input. See Table 5. LFMODE 36 I, LVCMOS w/ pull-down SSCG Low Frequency Mode — Pin or Register Control LF_MODE = 1, low frequency mode (TxCLKOUT = 10–20 MHz) LF_MODE = 0, high frequency mode (TxCLKOUT = 20–65 MHz) SSCG not avaialble above 65 MHz. MAPSEL 34 I, LVCMOS w/ pull-down Channel Link Map Select — Pin or Register Control MAPSEL = 1, MSB on TxOUT3+/-. MAPSEL = 0, LSB on TxOUT3+/-. CONFIG [1:0] 11, 10 I, LVCMOS w/ pull-down Operating Modes — Pin or Limited Register Control Determine the device operating mode and interfacing device. CONFIG[1:0] = 00: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter DISABLED CONFIG[1:0] = 01: Interfacing to DS92LV2421 or DS92LV0421, Control Signal Filter ENABLED CONFIG [1:0] = 10: Interfacing to DS90UR241, DS99R421 CONFIG [1:0] = 11: Interfacing to DS90C124 SSC[2:0] 7, 2, 3 I, LVCMOS w/ pull-down Spread Spectrum Clock Generation (SSCG) Range Select See Table 8 Table 9 RES 37 I, LVCMOS w/ pull-down Reserved Control and Configuration — STRAP PIN EQ 28 [PASS] STRAP I, LVCMOS w/ pull-down EQ Gain Control of Channel Link II Serial Input EQ = 1, EQ gain is enabled (~13 dB) EQ = 0, EQ gain is disabled (~1.625 dB) Optional BIST Mode BISTEN 29 I, LVCMOS w/ pull-down BIST Mode — Optional BISTEN = 1, BIST is enabled BISTEN = 0, BIST is disabled PASS 28 O, LVCMOS PASS Output (BIST Mode) — Optional PASS =1, no errors detected PASS = 0, errors detected Leave open if unused. Route to a test point (pad) recommended. www.national.com 6 |
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