Electronic Components Datasheet Search |
|
DS92LV2412SQX Datasheet(PDF) 4 Page - National Semiconductor (TI) |
|
|
DS92LV2412SQX Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 40 page DS92LV2411 Serializer Pin Descriptions Pin Name Pin # I/O, Type Description LVCMOS Parallel Interface DI[7:0] 34, 33, 32, 29, 28, 27, 26, 25 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB. DI[15:8] 42, 41, 40, 39, 38, 37, 36, 35 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB. DI[23:16] 2, 1, 48, 47, 46, 45, 44, 43 I, LVCMOS w/ pull-down Parallel Interface Data Input Pins For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB. CI1 5 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI1 = Data Enable Input Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. CI2 3 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI2 = Horizontal Sync Input Control signal pulse width must be 3 clocks or longer to be transmitted when the Control Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter setting. CI3 4 I, LVCMOS w/ pull-down Control Signal Input For Display/Video Application: CI3 = Vertical Sync Input CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is 130 clock cycle wide. CLKIN 10 I, LVCMOS w/ pull-down Clock Input Latch/data strobe edge set by RFB pin. Control and Configuration PDB 21 I, LVCMOS w/ pull-down Power-down Mode Input PDB = 1, Ser is enabled (normal operation). Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section. PDB = 0, Ser is powered down When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are RESET. VODSEL 24 I, LVCMOS w/ pull-down Differential Driver Output Voltage Select VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low power mode. This is can also be control by I2C register. De-Emph 23 I, Analog w/ pull-up De-Emphasis Control De-Emph = open (float) - disabled To enable De-emphasis, tie a resistor from this pin to GND or control via register. See Table 3. This can also be controlled by I2C register access. RFB 11 I, LVCMOS w/ pull-down Clock Input Latch/Data Strobe Edge Select RFB = 1, parallel interface data and control signals are latched on the rising clock edge. RFB = 0, parallel interface data and control signals are latched on the falling clock edge. This can also be controlled by I2C register access. www.national.com 4 |
Similar Part No. - DS92LV2412SQX |
|
Similar Description - DS92LV2412SQX |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |