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C8051F714-GQ Datasheet(PDF) 5 Page - Silicon Laboratories |
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C8051F714-GQ Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 290 page Rev. 0.3 5 C8051F70x/71x 20.4.1. VDD Maintenance and the VDD Monitor .............................................. 136 20.4.2. PSWE Maintenance .............................................................................. 136 20.4.3. System Clock ........................................................................................ 137 21. EEPROM ............................................................................................................... 140 21.1. RAM Reads and Writes ................................................................................. 140 21.2. Auto Increment .............................................................................................. 140 21.3. Interfacing with the EEPROM........................................................................ 140 21.4. EEPROM Security ......................................................................................... 141 22. Power Management Modes................................................................................. 145 22.1. Idle Mode....................................................................................................... 145 22.2. Stop Mode ..................................................................................................... 146 22.3. Suspend Mode .............................................................................................. 146 23. Reset Sources ...................................................................................................... 148 23.1. Power-On Reset ............................................................................................ 149 23.2. Power-Fail Reset / VDD Monitor ................................................................... 150 23.3. External Reset ............................................................................................... 151 23.4. Missing Clock Detector Reset ....................................................................... 151 23.5. Comparator0 Reset ....................................................................................... 152 23.6. Watchdog Timer Reset.................................................................................. 152 23.7. Flash Error Reset .......................................................................................... 152 23.8. Software Reset .............................................................................................. 152 24. Watchdog Timer................................................................................................... 154 24.1. Enable/Reset WDT........................................................................................ 154 24.2. Disable WDT ................................................................................................. 154 24.3. Disable WDT Lockout.................................................................................... 154 24.4. Setting WDT Interval ..................................................................................... 154 25. Oscillators and Clock Selection ......................................................................... 156 25.1. System Clock Selection................................................................................. 156 25.2. Programmable Internal High-Frequency (H-F) Oscillator .............................. 158 25.3. External Oscillator Drive Circuit..................................................................... 160 25.3.1. External Crystal Example...................................................................... 162 25.3.2. External RC Example............................................................................ 163 25.3.3. External Capacitor Example.................................................................. 164 26. Port Input/Output ................................................................................................. 165 26.1. Port I/O Modes of Operation.......................................................................... 166 26.1.1. Port Pins Configured for Analog I/O...................................................... 166 26.1.2. Port Pins Configured For Digital I/O...................................................... 166 26.1.3. Interfacing Port I/O to 5 V Logic ............................................................ 167 26.1.4. Increasing Port I/O Drive Strength ........................................................ 168 26.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 168 26.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 168 26.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 169 26.2.3. Assigning Port I/O Pins to External Event Trigger Functions................ 169 26.3. Priority Crossbar Decoder ............................................................................. 170 26.4. Port I/O Initialization ...................................................................................... 172 |
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