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LTC4269-2 Datasheet(PDF) 11 Page - Linear Technology

Part # LTC4269-2
Description  IEEE 802.3at High Power PD and Synchronous Forward Controller with AUX Support
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4269-2 Datasheet(HTML) 11 Page - Linear Technology

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LTC4269-2

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OC (Pin 19): OC is an accurate 107mV threshold, indepen-
dent of duty cycle, for overcurrent detection and trigger of
soft-start. Connect this pin directly to the sense resistor
in the source of the external power MOSFET.
DELAY (Pin 20): A resistor to GND adjusts the delay period
between SOUT rising edge and OUT rising edge. Used to
maximize efficiency in forward converter applications by
adjustingthetiming.Increasingtheresistorvalueincreases
the delay period.
PGND (Pin 21): Power Ground. Carries the gate driver’s
return current. Tie to VNEG.
OUT (Pin 22): Drives the gate of an N-channel MOSFET
between 0V and VIN with a maximum limit of 13V on
OUT pin set by an internal clamp. Active pull-off exists in
shutdown (see electrical specification).
VIN(Pin23):InputSupplyforthePowerSupplyController.It
mustbecloselydecoupledtoGND.Aninternalundervoltage
lockout threshold exists for VIN at approximately 14.25V
on and 8.75V off.
SOUT (Pin 24): Switched Output in Phase with OUT Pin.
Provides sync signal for control of secondary-side FETs
in forward converter applications requiring highly efficient
synchronous rectification. SOUT is actively clamped to
12V. Active pull-off exists in shutdown (see electrical
specification). Can also be used to drive the active clamp
FET of an active clamp forward supply.
pin FuncTions
VNEG (Pins 26, 27): Power Output. Connects the PoE
return line to the power supply through the internal Hot
Swap power MOSFET. Pins 26 and 27 must be electrically
tied together at the package.
PWRGD (Pin 28): Active High Power Good Output, Open
Collector. Signals that the internal Hot Swap MOSFET is
on. High Impedance indicates power is good. PWRGD is
referenced to VNEG and is low impedance during inrush
and in the event of thermal overload. PWRGD is clamped
14V above VNEG.
PWRGD (Pin 29): Active Low Power Good Output, Open
Drain. Signals that the internal Hot Swap MOSFET is
on. Low Impedance indicates power is good. PWRGD
is referenced to VPORTN and is high impedance during
inrush and in the event of thermal overload. PWRGD has
no internal clamps.
VPORTP (Pin 32): Input Voltage Positive Rail. This pin is
connected to the PD’s positive rail.
Exposed Pad (Pin 33): Tie to GND and PCB heat sink.


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