Technical Note

4/15

BD8918F,BD8918FV,BD8919F,BD8919FV

www.rohm.com

2010.4 - Rev.D

© 2009 ROHM Co., Ltd. All rights reserved.

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Pin Description

Pin No. Pin Name

I/O

Signal

Level

Pin Function

1

XTAL1

I

VDD

Crystal connection or input for external clock

2

XTAL2

O

VDD

Crystal connection (leave open pin when external clock source is used)

3

VDD

S

VDD

3.3 V power source pin for host interface.

Connect 0.1µF capacitor between the VDD and GND pins.

4

CLKSEL

I

VDD

Input for clock frequency

division setting.

Pulled down to GND

with a 50k

 resistor.

BD8918F/FV H: 1/1 division; L: 1/2 division.

BD8919F/FV H: 1/2 division; L: 1/4 division.

5

RSTIN

I

VDD

Card reset signal input. Pulled down to GND with a 50k

 resistor.

6

IO_U

I/O

VDD

Host data I/O line; Pulled up to VDD with an 11k

 resistor

7

CGND

S

GND

GND

8

IO_C

I/O

VCC

I/O data line on the card side. Pulled up to VCC with an 11k

resistor.

9

RST

O

VCC

Card reset output

10

CLK

O

VCC

Card clock output

11

VCC

O

VCC

Card supply voltage. Connect 1µF capacitor between VCC and the CGND pins.

12

VDDP

S

VDDP

5V power source pin for card power feed. Connect 10µF capacitor between the

VDDP and CGND pins.

13

PRES

I

VDD

Card presence contact input (“H” active). Pulled up to VDD with a 50k

 resistor.

Connected to a switch where GND level is inputted when no card is inserted and

OPEN is inputted when a card is inserted. When “H” level is detected, a card is

assumed to be inserted and waits for the CMDVCCB input for the confirmation,

after the debounce time of typ. 8ms.

14

OFFB

O

VDD

Alarm output pin (“L” active).

NMOS open drain output. Pulled up to VDD with a 20k

 resistor.

15

CMDVCCB

I

VDD

Activation sequence command input; The activation sequence starts by signal

input (HL) from the host

16

GND

S

GND

GND

*Capacitors to be connected to VDD, VDDP and VCC should be placed immediately next to the pins (ESR<100m

).