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ADM1027ARQZ Datasheet(PDF) 3 Page - ON Semiconductor |
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ADM1027ARQZ Datasheet(HTML) 3 Page - ON Semiconductor |
3 / 56 page REV. A ADM1027 –3– Parameter Min Typ Max Unit Test Conditions/Comment OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL 0.4 V IOUT = –4.0 mA, VCC = 3.3 V High Level Output Current, IOH 0.1 1 mA VOUT = VCC SMBUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.4 V Hysteresis 500 mV DIGITAL INPUT LOGIC LEVELS (VID0–4) Input High Voltage, VIH 1.7 V Input Low Voltage, VIL 0.8 V DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH 2.0 V 5.5 V Maximum Input Voltage Input Low Voltage, VIL 0.8 V –0.3 V Minimum Input Voltage Hysteresis 0.5 V p-p DIGITAL INPUT CURRENT Input High Current, IIH –1 mA VIN = VCC Input Low Current, IIL 1 mA VIN = 0 Input Capacitance, CIN 5 pF SERIAL BUS TIMING Clock Frequency, fSCLK 10 100 kHz See Figure 1 Glitch Immunity, tSW 50 ns See Figure 1 Bus Free Time, tBUF 4.7 ms See Figure 1 Start Setup Time, tSU;STA 4.7 ms See Figure 1 Start Hold Time, tHD;STA 4.0 ms See Figure 1 SCL Low Time, tLOW 4.7 ms See Figure 1 SCL High Time, tHIGH 4.0 50 ms See Figure 1 SCL, SDA Rise Time, tr 1000 ns See Figure 1 SCL, SDA Fall Time, tf 300 ms See Figure 1 Data Setup Time, tSU;DAT 250 ns See Figure 1 Data Hold Time, tHD;DAT 300 ns See Figure 1 Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can Be Optionally Disabled NOTES 1All voltages are measured with respect to GND, unless otherwise specified. 2Typicals are at T A = 40 rC and represent the most likely parametric norm. 3Logic inputs will accept input high voltages up to V MAX even when the device is operating down to V MIN. 4Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. Specifications subject to change without notice. Rev. 3 | Page 3 of 56 | www.onsemi.com |
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